T4/USB: Add USB 2.0 UTMI dual phy support

T4240 internal UTMI phy is different comparing to previous UTMI PHY
in P3041.
This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for
T4240.
The phy timing is very sensitive and moving the phy enable code to
cpu_init.c will not work.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 7267611cbccfb2ffe942234ff32f3fbb12350266..6c02033f7138ef4fbbe0393674c9f1f071c7a7f9 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -537,8 +537,7 @@
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_A004468
 #define CONFIG_SYS_FSL_ERRATUM_A_004934

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 3711f518a40f0184987ba203efa311b208aaf8fb..74cc94be325a15c5e437d226fe5adff8db6d29f8 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2828,12 +2828,53 @@ typedef struct ccsr_pme {
        u8      res4[0x400];
 } ccsr_pme_t;
 
+#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+struct ccsr_usb_port_ctrl {
+       u32     ctrl;
+       u32     drvvbuscfg;
+       u32     pwrfltcfg;
+       u32     sts;
+       u8      res_14[0xc];
+       u32     bistcfg;
+       u32     biststs;
+       u32     abistcfg;
+       u32     abiststs;
+       u8      res_30[0x10];
+       u32     xcvrprg;
+       u32     anaprg;
+       u32     anadrv;
+       u32     anasts;
+};
+
+typedef struct ccsr_usb_phy {
+       u32     id;
+       struct  ccsr_usb_port_ctrl port1;
+       u8      res_50[0xc];
+       u32     tvr;
+       u32     pllprg[4];
+       u8      res_70[0x4];
+       u32     anaccfg;
+       u32     dbg;
+       u8      res_7c[0x4];
+       struct  ccsr_usb_port_ctrl port2;
+       u8      res_dc[0x334];
+} ccsr_usb_phy_t;
+
+#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
+#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
+#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
+#else
 typedef struct ccsr_usb_phy {
        u8      res0[0x18];
        u32     usb_enable_override;
        u8      res[0xe4];
 } ccsr_usb_phy_t;
 #define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
+#endif
 
 #ifdef CONFIG_SYS_FSL_RAID_ENGINE
 struct ccsr_raide {

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index f54b4089662d8cf472ff39f7f3d230987d630228..77c41f3c3e4e0c9ffed8bac7c3520470b418d956 100644 (file)
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -89,6 +89,27 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 
        if (!strcmp(phy_type, "utmi")) {
 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
+#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
+               ccsr_usb_phy_t *usb_phy =
+                       (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
+               setbits_be32(&usb_phy->pllprg[1],
+                            CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN     |
+                            CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN     |
+                            CONFIG_SYS_FSL_USB_PLLPRG2_MFI             |
+                            CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
+               setbits_be32(&usb_phy->port1.ctrl,
+                            CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
+               setbits_be32(&usb_phy->port1.drvvbuscfg,
+                            CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
+               setbits_be32(&usb_phy->port1.pwrfltcfg,
+                            CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
+               setbits_be32(&usb_phy->port2.ctrl,
+                            CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
+               setbits_be32(&usb_phy->port2.drvvbuscfg,
+                            CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
+               setbits_be32(&usb_phy->port2.pwrfltcfg,
+                            CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
+#endif
                setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
                setbits_be32(&ehci->control, UTMI_PHY_EN);
                udelay(1000); /* delay required for PHY Clk to appear */