imx8mm: clock: fix fracpll decode issue

The fracpll decoding is using the bit definitions for int pll. Most of
them are same, but the CLKE bit is different. Fix the wrong CLKE_MASK
for fracpll and correct all bit definitions in fracpll decoding.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
index 84ed61d21ebfcb729b610803be104e2431e9e6ea..140e8bbabd7b7252cd00884f75c381e6aad5bea7 100644 (file)
--- a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
+++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
@@ -19,7 +19,7 @@
 
 #define LOCK_STATUS    BIT(31)
 #define LOCK_SEL_MASK  BIT(29)
-#define CLKE_MASK      BIT(11)
+#define CLKE_MASK      BIT(13)
 #define RST_MASK       BIT(9)
 #define BYPASS_MASK    BIT(4)
 #define        MDIV_SHIFT      12

diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index d123ba1625b6e1e63abe25b28dfe0bf9cf501bec..91c827f6c01fdcd255b057ffbede5f11be98f9c7 100644 (file)
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -447,34 +447,34 @@ static u32 decode_fracpll(enum clk_root_src frac_pll)
        }
 
        /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
-       if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
+       if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0)
                return 0;
 
-       if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
+       if ((pll_gnrl_ctl & RST_MASK) == 0)
                return 0;
        /*
         * When BYPASS is equal to 1, PLL enters the bypass mode
         * regardless of the values of RESETB
         */
-       if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
+       if (pll_gnrl_ctl & BYPASS_MASK)
                return 24000000u;
 
-       if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
+       if (!(pll_gnrl_ctl & LOCK_STATUS)) {
                puts("pll not locked\n");
                return 0;
        }
 
-       if (!(pll_gnrl_ctl & INTPLL_CLKE_MASK))
+       if (!(pll_gnrl_ctl & CLKE_MASK))
                return 0;
 
-       main_div = (pll_fdiv_ctl0 & INTPLL_MAIN_DIV_MASK) >>
-               INTPLL_MAIN_DIV_SHIFT;
-       pre_div = (pll_fdiv_ctl0 & INTPLL_PRE_DIV_MASK) >>
-               INTPLL_PRE_DIV_SHIFT;
-       post_div = (pll_fdiv_ctl0 & INTPLL_POST_DIV_MASK) >>
-               INTPLL_POST_DIV_SHIFT;
+       main_div = (pll_fdiv_ctl0 & MDIV_MASK) >>
+               MDIV_SHIFT;
+       pre_div = (pll_fdiv_ctl0 & PDIV_MASK) >>
+               PDIV_SHIFT;
+       post_div = (pll_fdiv_ctl0 & SDIV_MASK) >>
+               SDIV_SHIFT;
 
-       k = pll_fdiv_ctl1 & GENMASK(15, 0);
+       k = pll_fdiv_ctl1 & KDIV_MASK;
 
        return lldiv((main_div * 65536 + k) * 24000000ULL,
                     65536 * pre_div * (1 << post_div));