malta: Allow MIPS64 builds

Both real Malta boards & emulators that mimic Malta (eg. QEMU) can
support MIPS64 CPUs. Allow MIPS64 builds of U-Boot for such boards,
which enables the user to make use of the whole 64 bit address space.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 53363e38fe4309fa751716ce1d25a12d6d0e3d58..abaeaf0330be8ef656f5e2dfdcaae4d47661fc28 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -33,6 +33,9 @@ config TARGET_MALTA
        select SUPPORTS_CPU_MIPS32_R1
        select SUPPORTS_CPU_MIPS32_R2
        select SUPPORTS_CPU_MIPS32_R6
+       select SUPPORTS_CPU_MIPS64_R1
+       select SUPPORTS_CPU_MIPS64_R2
+       select SUPPORTS_CPU_MIPS64_R6
        select SWAP_IO_SPACE
        select MIPS_L1_CACHE_SHIFT_6
 

diff --git a/board/imgtec/malta/Kconfig b/board/imgtec/malta/Kconfig
index 2bb8e8be16e2077376613d828a1dafcfa8fcafe0..98eb4d16c71762f9976a8df5475a2c7669f4d582 100644 (file)
--- a/board/imgtec/malta/Kconfig
+++ b/board/imgtec/malta/Kconfig
@@ -10,6 +10,7 @@ config SYS_CONFIG_NAME
        default "malta"
 
 config SYS_TEXT_BASE
-       default 0xbe000000
+       default 0xbe000000 if 32BIT
+       default 0xffffffffbe000000 if 64BIT
 
 endif

diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S
index 534db1d83245b010a086fc8523741ce2235068cd..3d48cdc1f4714ec05805c49a857197b51bc3a214 100644 (file)
--- a/board/imgtec/malta/lowlevel_init.S
+++ b/board/imgtec/malta/lowlevel_init.S
@@ -10,6 +10,7 @@
 #include <pci.h>
 
 #include <asm/addrspace.h>
+#include <asm/asm.h>
 #include <asm/regdef.h>
 #include <asm/malta.h>
 #include <asm/mipsregs.h>
@@ -34,7 +35,7 @@ lowlevel_init:
        mtc0    t0, CP0_CONFIG, 2
 
        /* detect the core card */
-       li      t0, KSEG1ADDR(MALTA_REVISION)
+       PTR_LI  t0, CKSEG1ADDR(MALTA_REVISION)
        lw      t0, 0(t0)
        srl     t0, t0, MALTA_REVISION_CORID_SHF
        andi    t0, t0, (MALTA_REVISION_CORID_MSK >> \
@@ -68,12 +69,12 @@ lowlevel_init:
         */
 _gt64120:
        /* move GT64120 registers from 0x14000000 to 0x1be00000 */
-       li      t1, KSEG1ADDR(GT_DEF_BASE)
+       PTR_LI  t1, CKSEG1ADDR(GT_DEF_BASE)
        li      t0, CPU_TO_GT32(0xdf000000)
        sw      t0, GT_ISD_OFS(t1)
 
        /* setup MEM-to-PCI0 mapping */
-       li      t1, KSEG1ADDR(MALTA_GT_BASE)
+       PTR_LI  t1, CKSEG1ADDR(MALTA_GT_BASE)
 
        /* setup PCI0 io window to 0x18000000-0x181fffff */
        li      t0, CPU_TO_GT32(0xc0000000)
@@ -100,7 +101,7 @@ _gt64120:
         */
 _msc01:
        /* setup peripheral bus controller clock divide */
-       li      t0, KSEG1ADDR(MALTA_MSC01_PBC_BASE)
+       PTR_LI  t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE)
        li      t1, 0x1 << MSC01_PBC_CLKCFG_SHF
        sw      t1, MSC01_PBC_CLKCFG_OFS(t0)
 
@@ -122,7 +123,7 @@ _msc01:
        sw      t1, MSC01_PBC_CS0CFG_OFS(t0)
 
        /* setup basic address decode */
-       li      t0, KSEG1ADDR(MALTA_MSC01_BIU_BASE)
+       PTR_LI  t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
        li      t1, 0x0
        li      t2, -CONFIG_SYS_MEM_SIZE
        sw      t1, MSC01_BIU_MCBAS1L_OFS(t0)
@@ -157,7 +158,7 @@ _msc01:
        sw      t2, MSC01_BIU_IP3MSK2L_OFS(t0)
 
        /* setup PCI memory */
-       li      t0, KSEG1ADDR(MALTA_MSC01_PCI_BASE)
+       PTR_LI  t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE)
        li      t1, MALTA_MSC01_PCIMEM_BASE
        li      t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK
        li      t3, MALTA_MSC01_PCIMEM_MAP

diff --git a/include/configs/malta.h b/include/configs/malta.h
index a36967848c56580f0bcdb826b024df80e393b9fd..fc4baba7d7ed212aa6aff756e2d39d4c53cac3e6 100644 (file)
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -39,14 +39,18 @@
  */
 #define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_TEXT_BASE
 
-#define CONFIG_SYS_SDRAM_BASE          0x80000000 /* Cached addr */
+#ifdef CONFIG_64BIT
+# define CONFIG_SYS_SDRAM_BASE         0xffffffff80000000
+#else
+# define CONFIG_SYS_SDRAM_BASE         0x80000000
+#endif
 #define CONFIG_SYS_MEM_SIZE            (256 * 1024 * 1024)
 
 #define CONFIG_SYS_INIT_SP_OFFSET      0x400000
 
-#define CONFIG_SYS_LOAD_ADDR           0x81000000
-#define CONFIG_SYS_MEMTEST_START       0x80100000
-#define CONFIG_SYS_MEMTEST_END         0x80800000
+#define CONFIG_SYS_LOAD_ADDR           (CONFIG_SYS_SDRAM_BASE + 0x01000000)
+#define CONFIG_SYS_MEMTEST_START       (CONFIG_SYS_SDRAM_BASE + 0x00100000)
+#define CONFIG_SYS_MEMTEST_END         (CONFIG_SYS_SDRAM_BASE + 0x00800000)
 
 #define CONFIG_SYS_MALLOC_LEN          (128 * 1024)
 #define CONFIG_SYS_BOOTPARAMS_LEN      (128 * 1024)
@@ -69,7 +73,11 @@
 /*
  * Flash configuration
  */
-#define CONFIG_SYS_FLASH_BASE          0xbe000000
+#ifdef CONFIG_64BIT
+# define CONFIG_SYS_FLASH_BASE         0xffffffffbe000000
+#else
+# define CONFIG_SYS_FLASH_BASE         0xbe000000
+#endif
 #define CONFIG_SYS_MAX_FLASH_BANKS     1
 #define CONFIG_SYS_MAX_FLASH_SECT      128
 #define CONFIG_SYS_FLASH_CFI