armv8/fsl-lsch2: Implement workaround for PIN MUX erratum A010539

Pin mux logic has 2 options in priority order, one is through RCW_SRC
and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic
takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT
to control the SPI muxing. But actually those are DSPI controller's
pads instead of QSPI controller's, so this workaround allows RCW
fields SPI_BASE and SPI_EXT to control relevant pads muxing.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index f8057baa031b6a6c1ca4dd6c9cd1ccd55c3e48dd..5a4c84418ee136fe5f5441af1b27fc74895dbc1f 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -6,12 +6,17 @@ config ARCH_LS1012A
 config ARCH_LS1043A
        bool "Freescale Layerscape LS1043A SoC"
        select SYS_FSL_ERRATUM_A010315
+       select SYS_FSL_ERRATUM_A010539
 
 config ARCH_LS1046A
        bool "Freescale Layerscape LS1046A SoC"
+       select SYS_FSL_ERRATUM_A010539
 
 config SYS_FSL_MMDC
        bool "Freescale Multi Mode DDR Controller"
 
 config SYS_FSL_ERRATUM_A010315
        bool "Workaround for PCIe erratum A010315"
+
+config SYS_FSL_ERRATUM_A010539
+       bool "Workaround for PIN MUX erratum A010539"

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index aa6a1849d4d351353d5ecd0a12e2aec45a3df491..d68eeba349a13ca9fd15ea34387ef072fc378e62 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -320,6 +320,19 @@ void erratum_a010315(void)
 }
 #endif
 
+static void erratum_a010539(void)
+{
+#if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+       u32 porsr1;
+
+       porsr1 = in_be32(&gur->porsr1);
+       porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
+       out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
+                porsr1);
+#endif
+}
+
 void fsl_lsch2_early_init_f(void)
 {
        struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -353,6 +366,7 @@ void fsl_lsch2_early_init_f(void)
        erratum_a008850_early(); /* part 1 of 2 */
        erratum_a009929();
        erratum_a009660();
+       erratum_a010539();
 }
 #endif
 

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 3d00909b2cf0894a7cc2f749fce60be5bd6e0edb..d88543d0634c8a44d7bcffe5b2e3b0c4fc96ff1d 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -168,6 +168,8 @@ struct sys_info {
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
 
 /* Device Configuration and Pin Control */
+#define DCFG_DCSR_PORCR1               0x0
+
 struct ccsr_gur {
        u32     porsr1;         /* POR status 1 */
 #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK      0xFF800000