]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
pwm: Add DT documentation for SiFive PWM Controller
authorYash Shah <yash.shah@sifive.com>
Thu, 23 Apr 2020 11:27:15 +0000 (16:57 +0530)
committerHeiko Schocher <hs@denx.de>
Thu, 9 Jul 2020 04:03:02 +0000 (06:03 +0200)
DT documentation for PWM controller added from Linux v5.6

commit: daa78cc3408e
("pwm: sifive: Add DT documentation for SiFive PWM Controller")

Signed-off-by: Yash Shah <yash.shah@sifive.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
doc/device-tree-bindings/pwm/pwm-sifive.txt [new file with mode: 0644]

diff --git a/doc/device-tree-bindings/pwm/pwm-sifive.txt b/doc/device-tree-bindings/pwm/pwm-sifive.txt
new file mode 100644 (file)
index 0000000..9a98837
--- /dev/null
@@ -0,0 +1,31 @@
+SiFive PWM controller
+
+Unlike most other PWM controllers, the SiFive PWM controller currently only
+supports one period for all channels in the PWM. All PWMs need to run at
+the same period. The period also has significant restrictions on the values
+it can achieve, which the driver rounds to the nearest achievable period.
+PWM RTL that corresponds to the IP block version numbers can be found
+here:
+
+https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
+
+Required properties:
+- compatible: Should be "sifive,<chip>-pwm" and "sifive,pwm<version>".
+  Supported compatible strings are: "sifive,fu540-c000-pwm" for the SiFive
+  PWM v0 as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
+  SiFive PWM v0 IP block with no chip integration tweaks.
+- reg: physical base address and length of the controller's registers
+- clocks: Should contain a clock identifier for the PWM's parent clock.
+- #pwm-cells: Should be 3.
+- interrupts: one interrupt per PWM channel
+
+Examples:
+
+pwm:  pwm@10020000 {
+       compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
+       reg = <0x0 0x10020000 0x0 0x1000>;
+       clocks = <&tlclk>;
+       interrupt-parent = <&plic>;
+       interrupts = <42 43 44 45>;
+       #pwm-cells = <3>;
+};