]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
phy: ti-pip3-phy: Add support for USB3 PHY
authorVignesh R <vigneshr@ti.com>
Thu, 29 Nov 2018 09:57:38 +0000 (10:57 +0100)
committerMarek Vasut <marex@denx.de>
Fri, 7 Dec 2018 15:31:46 +0000 (16:31 +0100)
Add support to handle USB3 PHYs present on AM57xx/DRA7xx SoCs. This is
needed to move AM57xx to DM_USB.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
drivers/phy/ti-pipe3-phy.c

index b22bbaf985180fda6216bd92c6f8daa6d8f6f747..e7e78e3c56d71a6bc58dde0c80260b91d649fd7f 100644 (file)
@@ -141,7 +141,7 @@ static int omap_pipe3_dpll_program(struct omap_pipe3 *pipe3)
        omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
 
        val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
-       val &= ~PLL_SELFREQDCO_MASK;
+       val &= ~(PLL_SELFREQDCO_MASK | PLL_IDLE);
        val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
        omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
 
@@ -265,10 +265,13 @@ static int pipe3_exit(struct phy *phy)
                return -EBUSY;
        }
 
-       val = readl(pipe3->pll_reset_reg);
-       writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
-       mdelay(1);
-       writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
+       if (pipe3->pll_reset_reg) {
+               val = readl(pipe3->pll_reset_reg);
+               writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
+               mdelay(1);
+               writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
+       }
+
        return 0;
 }
 
@@ -331,9 +334,11 @@ static int pipe3_phy_probe(struct udevice *dev)
        if (!pipe3->power_reg)
                return -EINVAL;
 
-       pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
-       if (!pipe3->pll_reset_reg)
-               return -EINVAL;
+       if (device_is_compatible(dev, "ti,phy-pipe3-sata")) {
+               pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
+               if (!pipe3->pll_reset_reg)
+                       return -EINVAL;
+       }
 
        pipe3->dpll_map = (struct pipe3_dpll_map *)dev_get_driver_data(dev);
 
@@ -350,8 +355,19 @@ static struct pipe3_dpll_map dpll_map_sata[] = {
        { },                                    /* Terminator */
 };
 
+static struct pipe3_dpll_map dpll_map_usb[] = {
+       {12000000, {1250, 5, 4, 20, 0} },       /* 12 MHz */
+       {16800000, {3125, 20, 4, 20, 0} },      /* 16.8 MHz */
+       {19200000, {1172, 8, 4, 20, 65537} },   /* 19.2 MHz */
+       {20000000, {1000, 7, 4, 10, 0} },       /* 20 MHz */
+       {26000000, {1250, 12, 4, 20, 0} },      /* 26 MHz */
+       {38400000, {3125, 47, 4, 20, 92843} },  /* 38.4 MHz */
+       { },                                    /* Terminator */
+};
+
 static const struct udevice_id pipe3_phy_ids[] = {
        { .compatible = "ti,phy-pipe3-sata", .data = (ulong)&dpll_map_sata },
+       { .compatible = "ti,omap-usb3", .data = (ulong)&dpll_map_usb},
        { }
 };