clk: sunxi: Add Allwinner A83T CLK driver

Add initial clock driver for Allwinner A83T.

- Implement USB bus and USB clocks via ccu_clk_gate table
  for A83T, so it can accessed in common clk enable and
  disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
  for A83T, so it can accessed in common reset deassert
  and assert functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>

diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index 38ff99d34544f397e73c529a34bbee815429d7f5..90af70d171ca9172dca512f99a64b264e90727e6 100644 (file)
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -37,6 +37,13 @@ config CLK_SUN8I_A23
          This enables common clock driver support for platforms based
          on Allwinner A23/A33 SoC.
 
+config CLK_SUN8I_A83T
+       bool "Clock driver for Allwinner A83T"
+       default MACH_SUN8I_A83T
+       help
+         This enables common clock driver support for platforms based
+         on Allwinner A83T SoC.
+
 config CLK_SUN8I_H3
        bool "Clock driver for Allwinner H3/H5"
        default MACH_SUNXI_H3_H5

diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 6924897036ad116777d914d9e884dc474fa6dab4..4a254c8671e4675c7a94086ac53d6b1757368dd5 100644 (file)
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -10,5 +10,6 @@ obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
 obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
 obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
 obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
+obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o

diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
new file mode 100644 (file)
index 0000000..3160f7f
--- /dev/null
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/arch/ccu.h>
+#include <dt-bindings/clock/sun8i-a83t-ccu.h>
+#include <dt-bindings/reset/sun8i-a83t-ccu.h>
+
+static struct ccu_clk_gate a83t_gates[] = {
+       [CLK_BUS_OTG]           = GATE(0x060, BIT(24)),
+       [CLK_BUS_EHCI0]         = GATE(0x060, BIT(26)),
+       [CLK_BUS_EHCI1]         = GATE(0x060, BIT(27)),
+       [CLK_BUS_OHCI0]         = GATE(0x060, BIT(29)),
+
+       [CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
+       [CLK_USB_PHY1]          = GATE(0x0cc, BIT(9)),
+       [CLK_USB_HSIC]          = GATE(0x0cc, BIT(10)),
+       [CLK_USB_HSIC_12M]      = GATE(0x0cc, BIT(11)),
+       [CLK_USB_OHCI0]         = GATE(0x0cc, BIT(16)),
+};
+
+static struct ccu_reset a83t_resets[] = {
+       [RST_USB_PHY0]          = RESET(0x0cc, BIT(0)),
+       [RST_USB_PHY1]          = RESET(0x0cc, BIT(1)),
+       [RST_USB_HSIC]          = RESET(0x0cc, BIT(2)),
+
+       [RST_BUS_OTG]           = RESET(0x2c0, BIT(24)),
+       [RST_BUS_EHCI0]         = RESET(0x2c0, BIT(26)),
+       [RST_BUS_EHCI1]         = RESET(0x2c0, BIT(27)),
+       [RST_BUS_OHCI0]         = RESET(0x2c0, BIT(29)),
+};
+
+static const struct ccu_desc a83t_ccu_desc = {
+       .gates = a83t_gates,
+       .resets = a83t_resets,
+};
+
+static int a83t_clk_bind(struct udevice *dev)
+{
+       return sunxi_reset_bind(dev, ARRAY_SIZE(a83t_resets));
+}
+
+static const struct udevice_id a83t_clk_ids[] = {
+       { .compatible = "allwinner,sun8i-a83t-ccu",
+         .data = (ulong)&a83t_ccu_desc },
+       { }
+};
+
+U_BOOT_DRIVER(clk_sun8i_a83t) = {
+       .name           = "sun8i_a83t_ccu",
+       .id             = UCLASS_CLK,
+       .of_match       = a83t_clk_ids,
+       .priv_auto_alloc_size   = sizeof(struct ccu_priv),
+       .ops            = &sunxi_clk_ops,
+       .probe          = sunxi_clk_probe,
+       .bind           = a83t_clk_bind,
+};