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(parent: d91a652) | patch
serial: uartlite: Fix uninitialized ret in debug uartlite
authorAshok Reddy Soma <ashok.reddy.soma@xilinx.com>
Tue, 1 Dec 2020 07:34:47 +0000 (00:34 -0700)
committerMichal Simek <michal.simek@xilinx.com>
Mon, 4 Jan 2021 09:51:26 +0000 (10:51 +0100)
commite5e8bbd25a499e65e7403b0b054fe35abe5187b3
tree409b92d16db048cbd3dd2d7fb24eac4891014770tree | snapshot
parentd91a652cfd96e2c4217946a1839cf3c8c0523e85commit | diff
serial: uartlite: Fix uninitialized ret in debug uartlite

Endianness detection is checked against uninitialized ret variable.
Assign ret with read value from status register to fix this.

Fixes: 31a359f87eaa ("serial: uartlite: Add support to work with any endianness")
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers/serial/serial_xuartlite.c diff | blob | history
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