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(parent: 2d20f34) | patch
mtd: spi-nor-core: Add support for volatile QE bit
authorTakahiro Kuwano <Takahiro.Kuwano@infineon.com>
Tue, 29 Jun 2021 06:00:59 +0000 (15:00 +0900)
committerJagan Teki <jagan@amarulasolutions.com>
Tue, 29 Jun 2021 13:46:54 +0000 (19:16 +0530)
commita4aa9b7522dc67745795c1e2a76115a616da00ea
tree537eb3eb31207ffe61a8f3d74cc1e21088b0ea8btree | snapshot
parent2d20f344858265722452d06fe7a5f86ca736b86dcommit | diff
mtd: spi-nor-core: Add support for volatile QE bit

Some of Spansion/Cypress chips support volatile version of configuration
registers and it is recommended to update volatile registers in the field
application due to a risk of the non-volatile registers corruption by
power interrupt. This patch adds a function to set Quad Enable bit in CFR1
volatile.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
drivers/mtd/spi/spi-nor-core.c diff | blob | history
include/linux/mtd/spi-nor.h diff | blob | history
My U-Boot fork