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riscv: dts: jh7110: Add clock source from PLL
authorXingyu Wu <xingyu.wu@starfivetech.com>
Fri, 7 Jul 2023 10:50:09 +0000 (18:50 +0800)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Mon, 24 Jul 2023 05:21:06 +0000 (13:21 +0800)
commit6c4b50e6deb719726a04ca154a6361bd866398f5
tree8ccc2d154642e6b2e3f3a3b76a93e6957f495904tree | snapshot
parent005f9627d02e8ecab3c58c77889060e72f7fa25dcommit | diff
riscv: dts: jh7110: Add clock source from PLL

Change the PLL clock source from syscrg to sys_syscon child node.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi diff | blob | history
arch/riscv/dts/jh7110-u-boot.dtsi diff | blob | history
arch/riscv/dts/jh7110.dtsi diff | blob | history
My U-Boot fork