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ARM: k2g: Update PLL Multiplier and divider values
authorLokesh Vutla <lokeshvutla@ti.com>
Thu, 3 Nov 2016 10:05:02 +0000 (15:35 +0530)
committerTom Rini <trini@konsulko.com>
Sun, 13 Nov 2016 20:54:37 +0000 (15:54 -0500)
commit4d0fec0e69189bd81c09909fc4eb742c63d5d7ee
treeaa0689931712615a5c9d2292f7383e1d404816eatree | snapshot
parent8b01ebd8128821febd84ee0f413c16d6339678d6commit | diff
ARM: k2g: Update PLL Multiplier and divider values

Only a certain set of PLLM/D values are recommended to configure the DDR
at the required speeds for a given clock input frequency. Updating these
values as specified in Data Sheet[1] Table 5-18

[1] http://www.ti.com/lit/ds/symlink/66ak2g02.pdf

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
board/ti/ks2_evm/board_k2g.c diff | blob | history
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