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stm32mp1: clk: configure pll1 with OPP
authorPatrick Delaunay <patrick.delaunay@st.com>
Mon, 25 May 2020 10:19:44 +0000 (12:19 +0200)
committerPatrick Delaunay <patrick.delaunay@st.com>
Tue, 7 Jul 2020 14:01:23 +0000 (16:01 +0200)
commit37ad8377af00128adc47fb1192142ac9dfbf1f9d
tree99298fd93ebb907fe3d7f24587b8b88aa9f1cbedtree | snapshot
parent918e9c3d638722e5169091594846462e7af69f47commit | diff
stm32mp1: clk: configure pll1 with OPP

The PLL1 node (st,pll1) is optional in device tree, the max supported
frequency define in OPP node is used when the node is absent.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
doc/device-tree-bindings/clock/st,stm32mp1.txt diff | blob | history
drivers/clk/clk_stm32mp1.c diff | blob | history
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