From dec7c84227339cda4bf6c7d9a411ea189473112d Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai <wens@csie.org> Date: Tue, 23 Jun 2015 19:57:24 +0800 Subject: [PATCH] sunxi: rsb: Enable R_PIO clock before configuring external pins The original code was configuring the external pins after enabling the R_PIO clock, which meant the configuration never made it to the pin controller the first time in SPL. Why this was working before is uncertain. Maybe the state was left from a previous boot sequence, or RSB just happened to be the default configuration. However with some A33 chips, SPL failed to configure the PMIC. This was seen by me and Maxime on the Sinlinx SinA33 dev board. Reordering the calls fixed this. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> --- arch/arm/cpu/armv7/sunxi/rsb.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/rsb.c b/arch/arm/cpu/armv7/sunxi/rsb.c index f115a9cac4..6fd11f1529 100644 --- a/arch/arm/cpu/armv7/sunxi/rsb.c +++ b/arch/arm/cpu/armv7/sunxi/rsb.c @@ -60,11 +60,12 @@ int rsb_init(void) struct sunxi_rsb_reg * const rsb = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - rsb_cfg_io(); - /* Enable RSB and PIO clk, and de-assert their resets */ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB); + /* Setup external pins */ + rsb_cfg_io(); + writel(RSB_CTRL_SOFT_RST, &rsb->ctrl); rsb_set_clk(); -- 2.39.5