From c5b8412d60e22b49348a63848cbf7b6ab5ccb16e Mon Sep 17 00:00:00 2001 From: Paul Burton <paul.burton@imgtec.com> Date: Wed, 21 Sep 2016 11:18:57 +0100 Subject: [PATCH] MIPS: Ensure Config.K0=2 applies before any memory accesses During boot we set Config.K0=2 (uncached) such that any accesses to the kseg0 memory region are performed uncached before the caches are initialised. This write to the Config register introduces an execution hazard between it & any following memory accesses (such as the load of _gp), which we need to clear in order to ensure those memory accesses are actually performed uncached. Clear this execution hazard with the insertion of an ehb execution hazard barrier instruction. Signed-off-by: Paul Burton <paul.burton@imgtec.com> --- arch/mips/cpu/start.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index c157d03d31..8f85ede9ad 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -127,6 +127,7 @@ reset: and t0, t0, MIPS_CONF_IMPL or t0, t0, CONF_CM_UNCACHED mtc0 t0, CP0_CONFIG + ehb #endif /* -- 2.39.5