From aa51005c3f7e517164fa000d68672041f6c4191f Mon Sep 17 00:00:00 2001 From: Armando Visconti <armando.visconti@st.com> Date: Mon, 26 Mar 2012 00:09:55 +0000 Subject: [PATCH] net/designware: Consecutive writes must have delay This patch solves a TX/RX problem which happens at 10Mbps, due to the fact that we are not respecting 4 cyles of the phy_clk (2.5MHz) between two consecutive writes on the same register. Signed-off-by: Armando Visconti <armando.visconti@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> --- drivers/net/designware.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index fc14b70420..933032cfde 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -175,8 +175,7 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode); writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode); - writel(readl(&mac_p->conf) | RXENABLE, &mac_p->conf); - writel(readl(&mac_p->conf) | TXENABLE, &mac_p->conf); + writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); return 0; } -- 2.39.5