From a81d792479340bf03131111b285c0f70d27622b6 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Tue, 14 Feb 2023 19:35:26 +0200 Subject: [PATCH] ARM: tegra: clock: add clock_decode_pair helper Get periph clock id and its parent from device tree. This works by looking up the peripheral's 'clocks' node and reading out the second and fourth cells, which are the peripheral and PLL clock numbers. Tested-by: Andreas Westman Dorcsak # ASUS TF T30 Tested-by: Robert Eckelmann # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel # HTC One X Signed-off-by: Svyatoslav Ryhel Signed-off-by: Tom --- arch/arm/include/asm/arch-tegra/clock.h | 13 +++++++++++++ arch/arm/mach-tegra/clock.c | 23 +++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index 2270501406..61ef81e7fe 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -270,6 +270,19 @@ void clock_ll_start_uart(enum periph_id periph_id); */ int clock_decode_periph_id(struct udevice *dev); +/** + * Get periph clock id and its parent from device tree. + * + * This works by looking up the peripheral's 'clocks' node and reading out + * the second and fourth cells, which are the peripheral and PLL clock numbers. + * + * @param dev udevice associated with FDT node + * @param clk_id pointer to int array of 2 values + * first is periph clock, second is + * its PLL parent according to FDT. + */ +int clock_decode_pair(struct udevice *dev, int *clk_id); + /** * Checks if the oscillator bypass is enabled (XOBP bit) * diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 11bffc1701..966009f375 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -678,6 +678,29 @@ int clock_decode_periph_id(struct udevice *dev) assert(clock_periph_id_isvalid(id)); return id; } + +/* + * Get periph clock id and its parent from device tree. + * + * @param dev udevice associated with FDT node + * @param clk_id pointer to u32 array of 2 values + * first is periph clock, second is + * its PLL parent according to FDT. + */ +int clock_decode_pair(struct udevice *dev, int *clk_id) +{ + u32 cell[4]; + int err; + + err = dev_read_u32_array(dev, "clocks", cell, ARRAY_SIZE(cell)); + if (err) + return -EINVAL; + + clk_id[0] = clk_id_to_periph_id(cell[1]); + clk_id[1] = clk_id_to_pll_id(cell[3]); + + return 0; +} #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */ int clock_verify(void) -- 2.39.5