From 789b6dceccbb852b0be235334b713467f88e2f8e Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 11 May 2016 07:44:59 -0700
Subject: [PATCH] x86: Prepare configuration tables in dedicated high memory
region
Currently when CONFIG_SEABIOS is on, U-Boot allocates configuration
tables via normal malloc(). To simplify, use a dedicated memory
region which is reserved on the stack before relocation for this
purpose. Add functions for reserve and malloc.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
arch/x86/Kconfig | 14 ++++++++++++
arch/x86/include/asm/coreboot_tables.h | 19 ++++++++++++++++
arch/x86/include/asm/global_data.h | 4 ++++
arch/x86/lib/coreboot_table.c | 31 ++++++++++++++++++++++++++
4 files changed, 68 insertions(+)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 9d0f502161..2ba36b790c 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -531,6 +531,20 @@ config SEABIOS
Check http://www.seabios.org/SeaBIOS for details.
+config HIGH_TABLE_SIZE
+ hex "Size of configuration tables which reside in high memory"
+ default 0x10000
+ depends on SEABIOS
+ help
+ SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
+ configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
+ puts a copy of configuration tables in high memory region which
+ is reserved on the stack before relocation. The region size is
+ determined by this option.
+
+ Increse it if the default size does not fit the board's needs.
+ This is most likely due to a large ACPI DSDT table is used.
+
source "arch/x86/lib/efi/Kconfig"
endmenu
diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h
index 15ccf9be6c..e036f744f6 100644
--- a/arch/x86/include/asm/coreboot_tables.h
+++ b/arch/x86/include/asm/coreboot_tables.h
@@ -294,6 +294,25 @@ struct cbmem_entry {
#define CBMEM_ID_CONSOLE 0x434f4e53
#define CBMEM_ID_NONE 0x00000000
+/**
+ * high_table_reserve() - reserve configuration table in high memory
+ *
+ * This reserves configuration table in high memory.
+ *
+ * @return: always 0
+ */
+int high_table_reserve(void);
+
+/**
+ * high_table_malloc() - allocate configuration table in high memory
+ *
+ * This allocates configuration table in high memory.
+ *
+ * @bytes: size of configuration table to be allocated
+ * @return: pointer to configuration table in high memory
+ */
+void *high_table_malloc(size_t bytes);
+
/**
* write_coreboot_table() - write coreboot table
*
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index 3bc2ac24cf..7434f779b6 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -93,6 +93,10 @@ struct arch_global_data {
char *mrc_output;
unsigned int mrc_output_len;
ulong table; /* Table pointer from previous loader */
+#ifdef CONFIG_SEABIOS
+ u32 high_table_ptr;
+ u32 high_table_limit;
+#endif
};
#endif
diff --git a/arch/x86/lib/coreboot_table.c b/arch/x86/lib/coreboot_table.c
index cb45a79857..ceab3cf5e4 100644
--- a/arch/x86/lib/coreboot_table.c
+++ b/arch/x86/lib/coreboot_table.c
@@ -9,6 +9,37 @@
#include <asm/coreboot_tables.h>
#include <asm/e820.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+int high_table_reserve(void)
+{
+ /* adjust stack pointer to reserve space for configuration tables */
+ gd->arch.high_table_limit = gd->start_addr_sp;
+ gd->start_addr_sp -= CONFIG_HIGH_TABLE_SIZE;
+ gd->arch.high_table_ptr = gd->start_addr_sp;
+
+ /* clear the memory */
+ memset((void *)gd->arch.high_table_ptr, 0, CONFIG_HIGH_TABLE_SIZE);
+
+ gd->start_addr_sp &= ~0xf;
+
+ return 0;
+}
+
+void *high_table_malloc(size_t bytes)
+{
+ u32 new_ptr;
+ void *ptr;
+
+ new_ptr = gd->arch.high_table_ptr + bytes;
+ if (new_ptr >= gd->arch.high_table_limit)
+ return NULL;
+ ptr = (void *)gd->arch.high_table_ptr;
+ gd->arch.high_table_ptr = new_ptr;
+
+ return ptr;
+}
+
/**
* cb_table_init() - initialize a coreboot table header
*
--
2.39.5