From 55cdcdaad3edb24779b76716d5cf9c36db2fed44 Mon Sep 17 00:00:00 2001 From: Josh Marshall <josh.marshall@tecevo.com> Date: Fri, 30 Sep 2016 15:19:58 +1000 Subject: [PATCH] sunxi: OLinuXino Lime A20 boards: Use 384 MHz DRAM clock We have a number of OlinuXino Lime2 boards (both NAND and eMMC versions) which were experiencing sporadic hangs. After testing with some heavy benchmarking and help from the Armbian forum, it was pinned down as the DRAM settings for the board. The default is 480MHz, but this is unstable, and even the build instructions from the vendor Olimex themselves say to set the DRAM clock to 384. See line 96 at: https://github.com/OLIMEX/OLINUXINO/blob/master/SOFTWARE/A20/A20-build-3.4.103-release-2/BUILD_DESCRIPTION_A20_Olimex_kernel_3.4.103%2B_Jessie_rel_2.txt Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> --- configs/A20-OLinuXino-Lime2_defconfig | 2 +- configs/A20-OLinuXino-Lime_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig index 56886226df..4751fe0533 100644 --- a/configs/A20-OLinuXino-Lime2_defconfig +++ b/configs/A20-OLinuXino-Lime2_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_MACH_SUN7I=y -CONFIG_DRAM_CLK=480 +CONFIG_DRAM_CLK=384 CONFIG_MMC0_CD_PIN="PH1" CONFIG_USB0_VBUS_PIN="PC17" CONFIG_USB0_VBUS_DET="PH5" diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig index c4f6e1a9a2..024dc2d8a7 100644 --- a/configs/A20-OLinuXino-Lime_defconfig +++ b/configs/A20-OLinuXino-Lime_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_MACH_SUN7I=y -CONFIG_DRAM_CLK=480 +CONFIG_DRAM_CLK=384 CONFIG_MMC0_CD_PIN="PH1" CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -- 2.39.5