From 4fc495e9e2e497afee383294a6ee9212e9a8bd73 Mon Sep 17 00:00:00 2001
From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Date: Sat, 2 Dec 2017 00:19:14 +0100
Subject: [PATCH] rockchip: clk: rk3128: fix DCLK_VOP_DIV_CON_MASK
The DCLK_VOP_DIV_CON_MASK should cover only bits 8 through 15.
Fix this to remove an "integer-overflow on shifted constant" warning.
Fixes: 9246d9e ("rockchip: rk3128: add clock driver")
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
arch/arm/include/asm/arch-rockchip/cru_rk3128.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3128.h b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h
index 3d8317ed91..90012c7fce 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3128.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h
@@ -187,7 +187,7 @@ enum {
DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT,
DCLK_VOP_PLL_SEL_CPLL = 0,
DCLK_VOP_DIV_CON_SHIFT = 8,
- DCLK_VOP_DIV_CON_MASK = 0xfff << DCLK_VOP_DIV_CON_SHIFT,
+ DCLK_VOP_DIV_CON_MASK = 0xff << DCLK_VOP_DIV_CON_SHIFT,
/* CRU_CLKSEL31_CON */
VIO0_PLL_SHIFT = 5,
--
2.39.5