From 087bfe67ac2555c37b257335424b7c193d7f6afd Mon Sep 17 00:00:00 2001
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Thu, 23 May 2019 11:05:45 +0800
Subject: [PATCH] armv8: fsl-lsch3: add clock support for the second eSDHC
Layerscape began to use two eSDHC controllers, for example,
LS1028A. They are same IP block with same reference clock.
This patch is to add clock support for the second eSDHC.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 2 ++
arch/arm/include/asm/arch-fsl-layerscape/clock.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index bc268e207c..a5540f2b9d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014-2015, Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP Semiconductors
*
* Derived from arch/power/cpu/mpc85xx/speed.c
*/
@@ -214,6 +215,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
return get_i2c_freq(0);
#if defined(CONFIG_FSL_ESDHC)
case MXC_ESDHC_CLK:
+ case MXC_ESDHC2_CLK:
return get_sdhc_freq(0);
#endif
case MXC_DSPI_CLK:
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/clock.h b/arch/arm/include/asm/arch-fsl-layerscape/clock.h
index cf058d22a9..b37a08d265 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/clock.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/clock.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP Semiconductors
*
*/
@@ -14,6 +15,7 @@ enum mxc_clock {
MXC_BUS_CLK,
MXC_UART_CLK,
MXC_ESDHC_CLK,
+ MXC_ESDHC2_CLK,
MXC_I2C_CLK,
MXC_DSPI_CLK,
};
--
2.39.5