Nuno Sá [Thu, 11 May 2023 11:19:50 +0000 (13:19 +0200)]
mtd: cfi: respect reg address length
flash_get_size() will get the flash size from the device itself and go
through all erase regions to read protection status. However, the device
mappable region (eg: devicetree reg property) might be lower than the
device full size which means that the above cycle will result in a data
bus exception. This change fixes it by reading the 'addr_size' during
probe() and also use that as one possible upper limit.
Revert "spi: zynq_qspi: Use dummy buswidth in dummy byte calculation"
This reverts commit e09784728689de7949d4cdd559a9590e0bfcc702. The
commit wrongly divides the dummy bytes by dummy bus width to calculate
the dummy bytes. The framework already converts the dummy cycles to the
number of bytes and the controller use the SPI flash command to
determine the dummy cycles via the address width.
Michal Simek [Wed, 12 Apr 2023 14:30:27 +0000 (16:30 +0200)]
arm64: zynqmp: Fix User MTD partition size
The commit c8630167e0dc ("arm64: zynqmp: Add mtd partition for secure OS
storage area") didn't update User partition size that's why size was beyond
actual device size.
arm64: zynqmp: Fix issue of apps executing from R5 core 1
In current implementation, applications can execute only on R5 core 0.
The boot address for R5 core 1 is not supplied. Pass TCM address for
R5 core 1 based on the argument to fix the issue.
- Assorted bootstd fixes and cleanups. This should fix problems with
Debian, and make script-based distributions work when BOOTMETH_DISTRO
is enabled now (as BOOTMETH_DISTRO was renamed and then reintroduced).
Simon Glass [Wed, 10 May 2023 22:34:47 +0000 (16:34 -0600)]
bootstd: Create a new BOOTMETH_DISTRO
We cannot be sure what bootmeth a distro will need to use. Add a new
BOOTMETH_DISTRO option which collects these together. Select this from
BOOTSTD_DEFAULTS so that it is clear what is needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Make BOOTMETH_EFILOADER depend on EFI_LOADER, select if EFI_LOADER] Signed-off-by: Tom Rini <trini@konsulko.com>
Simon Glass [Wed, 10 May 2023 22:34:46 +0000 (16:34 -0600)]
bootstd: Rename distro and syslinux to extlinux
We use the terms 'distro' to mean extlinux but they are not really the
same. 'Distro' could refer to any method of booting a distribution,
whereas extlinux is a particular method.
Also we sometimes use syslinux, but it is better to use the same term in
all cases.
Rename distro to syslinux and also update bootstd uses of syslinux to use
extlinux instead.
Simon Glass [Wed, 10 May 2023 22:34:26 +0000 (16:34 -0600)]
bootstd: Tidy up reporting of errors
In a few cases the error handling is not quite right. Make sure we
return the actual error in distro_efi_read_bootflow_file() rather than
-EINVAL. Return -IO when a file cannot be read. Also show the error name
if available.
This does not change operation, but does make it easier to diagnose
problems.
Simon Glass [Sat, 6 May 2023 14:27:09 +0000 (08:27 -0600)]
bootstd: Correct default boot command
The patch to relax flag requirements was not accepted[1], so we still have
to have separate bootcommands depending on CMD_BOOTFLOW_FULL.
The previous attempt at this did not work, since it used the wrong name
for the options.
Fix this and change the message to mention BOOTSTD_FULL since this affects
not just the flags, but all functionality, so is more likely what the user
wants.
Drop the useless condition on CMD_BOOTFLOW_FULL while we are here.
Simon Glass [Fri, 28 Apr 2023 19:18:09 +0000 (13:18 -0600)]
bootstd: Work around missing partition 1
If there is no partition numbered 1, we decide that there are no
partitions at all. That may not be correct, since at least one Debian
installed has just a single partition numbered 2.
Continue searching up to partition 3, just in case.
The config file (spkgimage.cfg in this example) contains additional
parameters such as NAND ECC settings.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Ralph Siemsen [Sat, 13 May 2023 01:36:51 +0000 (21:36 -0400)]
clk: renesas: add R906G032 driver
Clock driver for the Renesas RZ/N1 SoC family. This is based on
Linux kernel 6.2.y drivers/clk/renesas/r9a06g032-clocks.c as found in
commit 02693e11611e ("clk: renesas: r9a06g032: Repair grave increment error"),
with the following additional patch series applied:
https://lore.kernel.org/linux-renesas-soc/20230301215520.828455-1-ralph.siemsen@linaro.org/
Notable difference: this version avoids allocating a 'struct clk'
for each clock source, as this is problematic before relocation.
Instead, it uses the same approach as existing Renesas R-Car Gen2/3
clock drivers, using a temporary structure filled on-the-fly.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Ralph Siemsen [Sat, 13 May 2023 01:36:50 +0000 (21:36 -0400)]
clk: renesas: prepare for non R-Car clock drivers
Add new CONFIG_CLK_RCAR to control compilation of shared code for R-Car
clock drivers (renesas-cpg-mssr.c). Enable this for R-Car Gen2 and 3.
This is necessary so that CONFIG_CLK_RENESAS can be enabled, allowing
recursion into the drivers/clk/reneasas directory, without bringing in
the R-Car support code. The support code contains platform specific
access (TMU_BASE) which is not needed on other Renesas devices such as
RZ/N1.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Ralph Siemsen [Sat, 13 May 2023 01:36:49 +0000 (21:36 -0400)]
ARM: armv7: add non-SPL enable for Cortex SMPEN
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Simon Glass [Thu, 4 May 2023 22:50:59 +0000 (16:50 -0600)]
x86: Simplify cpu_jump_to_64bit_uboot()
This copies the cpu_call64() function to memory address and then jumps to
it. This seems to work correctly even when called from SPL, which is
running from SPI flash.
Drop the copy as it is not needed.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:58 +0000 (16:50 -0600)]
spl: Commit MTRRs only in board_init_f_r()
We don't need to commit the SPI-flash MTRR change immediately, since it is
now done in the board_init_f_r(). Also this causes chromebook_link64 to
hang, presumably since we are still running from CAR (Cache-as-RAM) in
SPL. Coral handles this OK, perhaps since it is running from a different
memory area, but it has no effect on Coral anyway.
Drop the extra mtrr_commit() in the SPL implementation.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:57 +0000 (16:50 -0600)]
x86: spl: Avoid using init_cache_f_r() from SPL
This function is used by U-Boot proper. It does not set up MTRRs when SPL
is enabled, but we do want this done when it is called from SPL. In fact
it is confusing to use the same function from SPL, since there are quite
a few conditions there.
All init_cache_f_r() really does is commit the MTRRs and set up the cache.
Do this in the SPL's version of this function instead.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:55 +0000 (16:50 -0600)]
x86: Tidy up address for loading U-Boot from SPL
Use the binman symbols for this, to avoid hard-coding the value. We could
use CONFIG_X86_OFFSET_U_BOOT for the address, but it seems better to
obtain the offset and size through the same mechanism.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 9 May 2023 10:13:47 +0000 (18:13 +0800)]
x86: sysreset: Set up LPC only after relocation
Probing LPC can cause PCI enumeration to take place, which significantly
increases pre-relocation memory usage. Also, LPC is somtimes enabled
directly by SPL.
Adjust the logic to probe the LPC only after relocation. This allows
chromebook_link64 to start up without a much larger
CONFIG_SYS_MALLOC_F_LEN value.
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:52 +0000 (16:50 -0600)]
x86: Tidy up availability of string functions
For now, just enable the fast-but-large string functions in 32-boot
U-Boot proper only. Avoid using them in SPL. We cannot use then in 64-bit
builds since we only have 32-bit assembly.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 4 May 2023 22:50:48 +0000 (16:50 -0600)]
sf: Rename spi-nor-tiny functions
The 'tiny' SPI nor functions have the same name as their big brothers,
which can be confusing. Use different names so it is clear which
version is in the image.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:45 +0000 (16:50 -0600)]
dm: Emit the arch_cpu_init_dm() even only before relocation
The original function was only called once, before relocation. The new
one is called again after relocation. This was not the intent of the
original call. Fix this by renaming and updating the calling logic.
With this, chromebook_link64 makes it through SPL.
Fixes: 7fe32b3442f0 ("event: Convert arch_cpu_init_dm() to use events") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:55:01 +0000 (16:55 -0600)]
pci: coreboot: Don't read regions when booting
When U-Boot is the second-stage bootloader, PCI is already set up. We
cannot read the regions from the device tree. There is no point anyway,
since PCI devices have already been allocated according to the regions
and it is not safe for U-Boot to make any changes.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Fixes: f2ebaaa9f38d ("pci: Handle failed calloc in decode_regions()") Tested-by: Christian Gmeiner <christian.gmeiner@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:55:00 +0000 (16:55 -0600)]
x86: Allow locating the UART from ACPI tables
When coreboot does not pass a UART in its sysinfo struct, there is no
easy way to find it out.
Since coreboot does not actually init the serial device when serial is
disabled, it is not possible to make it add this information to the
sysinfo table.
Add a way to obtain this information from the DBG2 ACPI table, which is
normally set up by coreboot.
For now this only supports a memory-mapped 16550-style UART.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:54:59 +0000 (16:54 -0600)]
x86: coreboot: Collect the address of the ACPI tables
At present any ACPI tables created by prior-stage firmware are ignored.
It is useful to be able to view these in U-Boot.
Pick this up from the sysinfo tables and display it with the cbsysinfo
command. This allows the 'acpi list' command to work when booting from
coreboot.
Adjust the global_data condition so that acpi_start is available even if
table-generation is disabled.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:54:57 +0000 (16:54 -0600)]
acpi: Create a new Kconfig for ACPI
We have several Kconfig options for ACPI, but all relate to specific
functions, such as generating tables and AML code.
Add a new option which controls including basic ACPI library code,
including the lib/acpi directory. This will allow us to add functions
which are available even if table generation is not supported.
Adjust the command to avoid a build error when ACPIGEN is not enabled.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:54:56 +0000 (16:54 -0600)]
input: Flush the keyboard buffer before resetting it
If U-Boot is not the first-stage bootloader the keyboard may already be
set up. Make sure to flush any data before trying to reset it. This
avoids a long timeout / hang.
Add some comments and a log category while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:54:55 +0000 (16:54 -0600)]
x86: Adjust search range for sysinfo table
Avoid searching starting at 0 since this memory may not be available,
e.g. if protection against NULL-pointer access is enabled. The table
cannot be there anyway, since the first 1KB of memory was originally
used for the interrupt table and coreboot avoids it.
Start at 0x400 instead.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tom Rini [Tue, 9 May 2023 16:45:49 +0000 (12:45 -0400)]
Merge tag 'u-boot-rockchip-20230509' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Rockchip NFC driver update and dev addr pointer api update;
- use standard dr_mode for usb driver;
- rock pi boards dts update;
- Add rk3566 Anbernic boards;
- Misc fixes for drivers;
The CRU is being probed with a default set of assigned clocks, which
are not implemented in the driver at all.
Hence, when clk_set_defaults is called, it fails with ENOENT.
This would not be a problem, as the CRU still handles all the required
clocks, and the assigned clocks are default configs which are preprogrammed
or not required for Uboot operations.
However, the rockchip reset driver is being bound by the same DT node
as CRU, as the reset driver has no DT node.
But, when probing the reset node, it will call again the clk_set_defaults
for the CRU node, and failing because of missing those specific clocks
in the rk3588 clock driver.
To avoid this, simply implement a basic set/get that will just return
success and the default corresponding rate for the required assigned clocks.
As those clocks were not supported in Uboot, not required for Uboot
operations, there is no need to do any different kind of initialization.
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
John Keeping [Wed, 12 Apr 2023 11:52:53 +0000 (12:52 +0100)]
rockchip: handle peripheral as well as otg dr_mode
The OTG port is identified by inspecting the "dr_mode" property which is
expected to be "otg" for this port. But it will work just as well as a
device controller when dr_mode is set to "peripheral", which may be
required if the mode detection pin is not set up correctly and the
device controller needs to be programmed to override this.
Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Linux commit 246450344dad arm64: dts: rockchip: rk3399: Radxa ROCK 4C+
Add support for Radxa ROCK 4C+ SBC.
Key differences of 4C+ compared to previous ROCK Pi 4.
- Rockchip RK3399-T SoC
- DP from 4C replaced with micro HDMI 2K@60fps
- 4-lane MIPI DSI with 1920*1080
- RK817 Audio codec
Also, an official naming convention from Radxa mention to remove
Pi from board name, so this 4C+ is named as Radxa ROCK 4C+ not
Radxa ROCK Pi 4C+.
Signed-off-by: Stephen Chen <stephen@radxa.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
rockchip: rk3328: Add support for FriendlyARM NanoPi R2C
The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC
chip changed from rtl8211e to yt8521s, and otherwise identical to R2S.
The device tree is taken from the kernel linux-next branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=004589ff9df5b75672a78b6c3c4cba93202b14c9
Signed-off-by: Tianling Shen <cnsztl@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Eugen Hristev [Tue, 11 Apr 2023 07:20:40 +0000 (10:20 +0300)]
reset: reset-rockchip: fix trivial line spacing alignment
Fix line spacing aligment in bind function
Fixes: 760188c1aa5b ("rockchip: reset: support a (common) rockchip reset drivers") Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Eugen Hristev [Thu, 13 Apr 2023 14:11:03 +0000 (17:11 +0300)]
pci: pcie_dw_rockchip: release resources on failing probe
Implement a resource release mechanism on failing probe.
Without this, a strange situation can happen e.g. when init port fails,
or attempting to get the PHY fails, because the gpios have been
requested first, and if the user tries to do 'pci enum' again, the
driver will fail with 'can't find reset gpios' even if the gpios are
there, just because they were blocked by a previous probe attempt.
It is only natural to release the acquired resources if the probe fails,
just for consistency if nothing else.
This way on subsequent probe attempts, the user will get the same error
message, and not something different that doesn't make sense.
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The AM64x SR2.0 SK board uses "AM64B-SKEVM" as the EEPROM identifier.
This board is similar to the AM64x SKEVM except that it has a new
PMIC that will be enabled in the future and consequently could use a
different device tree file in the future.
For now we treat the board same as an AM64x SK.
Signed-off-by: Judith Mendez <jm@ti.com> Acked-by: Andrew Davis <afd@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
common: spl: spl: Remove video driver before u-boot proper
Add method to remove video driver before loading u-boot proper. When
bootstage changes from SPL to u-boot proper, noo method is called to
remove video driver, and at u-boot proper if video driver is not
enabled, the video driver starts displaying garbage on the screen,
because there is no reserved space for video and the frame buffer gets
u-boot proper data written.
To enable splash screen on AM62x at a53 SPL setup DRAM, set page table,
enable cache to allow copying of bmp image to frame buffer and display
it using splash_display.
board: ti: am62x: am62x: Change splashimage and splashsource
Change splashimage which is bmp image loadaddr to 0x80200000 since stack
is situated at 0x80477660 as splash framework requires bmp image to be
present above stack.
Change splashsource to sf to support loading bmp image from ospi flash
memory.
configs: am62x_evm_a53_defconfig: Changes in memory to support SPL splash screen
To enable splash at A53 SPL, need to do memory map changes which
involves locate stack above malloc and have enough space to load bmp
image above stack. To load a 1920X1200 image a minimum of 8.8MB space is
needed, to support it move malloc down to 0x80b80000 from 0x80480000 and
bss to 0x80c80000 to have 1MB buffer between malloc and BSS.
Observed SPL size 195KB, CONFIG_SPL_SIZE_LIMIT set to 256KB.
Observed stack size 1904Bytes, CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK set
to 2KB.
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE config sets stack above the malloc
and reports for stack overflow.
btrfs_read_extent_reg correctly computed the extent offset in the
BTRFS_COMPRESS_NONE case, but did not account for the 'offset - key.offset'
part correctly in the compressed case, making the function read
incorrect data.
In the case I examined, the last 4k of a file was corrupted and
contained data from a few blocks prior, e.g. reading a 10k file with a
single extent:
btrfs_file_read()
-> btrfs_read_extent_reg
(aligned part loop, until 8k)
-> read_and_truncate_page
-> btrfs_read_extent_reg
(re-reads the last extent from 8k to the end,
incorrectly reading the first 2k of data)
This can be reproduced as follow:
$ truncate -s 200M btr
$ mount btr -o compress /mnt
$ pat() { dd if=/dev/zero bs=1M count=$1 iflag=count_bytes status=none | tr '\0' "\\$2"; }
$ { pat 4K 1; pat 4K 2; pat 2K 3; } > /mnt/file
$ sync
$ filefrag -v /mnt/file
File size of /mnt/file is 10240 (3 blocks of 4096 bytes)
ext: logical_offset: physical_offset: length: expected: flags:
0: 0.. 2: 3328.. 3330: 3: last,encoded,eof
$ umount /mnt
Note that the code previously (before commit e3427184f38a ("fs: btrfs:
Implement btrfs_file_read()")) did not split that read in two, so
this is a regression even if the previous code might not have been
handling offsets correctly either (something that booted now fails to
boot)
Josua Mayer [Fri, 5 May 2023 08:20:49 +0000 (11:20 +0300)]
cmd: tlv_eeprom: enable 'dev' subcommand before 'read'
Move the handler for "tlv_eeprom dev X" command to the beginning of
do_tlv_eeprom, to allow using it before issuing a "read" command for
currently selected eeprom.
Also remove the check if eeprom exists, since that can only work after
the first execution of read_eeprom triggered device lookup.
Instead accept values up to the defined array size (MAX_TLV_DEVICES).
Signed-off-by: Josua Mayer <josua@solid-run.com> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Baruch Siach <baruch@tkos.co.il> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
The rk3566-anbernic-rgxx3.dtsi is synced with upstream Linux, but
rk3566-anbernic-rgxx3.dts is a U-Boot specific devicetree that
is used for all RGxx3 devices.
Via the board.c file, the bootloader automatically sets the correct
fdtfile, board, and board_name environment variables so that the
correct devicetree can be passed to Linux. It is also possible to
simply hard-code a single devicetree in the boot.scr file and use
that to load Linux as well.
The common specifications for each device are:
- Rockchip RK3566 SoC
- 2 external SDMMC slots
- 1 USB-C host port, 1 USB-C peripheral port
- 1 mini-HDMI output
- MIPI-DSI based display panel
- ADC controlled joysticks with a GPIO mux
- GPIO buttons
- A PWM controlled vibrator
- An ADC controlled button
All of the common features are defined in the devicetree synced from
upstream Linux.
TODO: DSI panel auto-detection for the RG353 devices (requires porting
of DSI controller driver and DSI-DPHY driver to send DSI commands to
the panel).
Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
rk3399: r4s: Derive local MAC address if EEPROM is missing
Some RK3399 boards, such as newer revisions of NanoPi R4S, do not
provide an EEPROM chip containing a globally unique MAC address.
Currently, this means that a randomly generated temporary MAC address
may be generated each time the device is rebooted, leading to ARP cache
issues and other confusing bugs.
Since RK3399 CPUs provide a built-in unique serial number, we can
reliably derive a locally MAC address from it by reading the
corresponding bits from the non-secure efuse block.
Enable configuration options that allow deriving a local MAC address
from the CPU serial number.
projects / u-boot.git / log
