Michal Simek [Wed, 27 Sep 2023 09:53:37 +0000 (11:53 +0200)]
arm64: zynqmp: Add support for zcu670-revB
RevB has different SD level shifter compare to revA. There are couple of
changes between revisions but none of them requires SW alignment.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0f2bb29f88615ce75f887c006060543b4aeafd48.1695808407.git.michal.simek@amd.com
Michal Simek [Wed, 27 Sep 2023 09:53:36 +0000 (11:53 +0200)]
arm64: zynqmp: Add support for zcu670-revA
The board is sharing a lot of components with zcu208 but it contains
differet silicon and also several components are done differently.
The board has 4GB memory connected to PS and additional 4GB connected to
PL. Compare to zcu208 sata support has been dropped and only USB3.0 is
using GTR (lane2). Others GTRs are routed to connectors.
MIO configuration is also shared with zcu111.
The board is using si5381 chip compare to si5341 which is normally used.
And as of now there is no Linux driver for this chip. PS reference clock is
generated out of si570 chip which is also new approach compare to zcu208.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3b296ef0f52bd94e32bdeb6d1beee29ac85f00a2.1695808407.git.michal.simek@amd.com
Michal Simek [Wed, 27 Sep 2023 09:53:35 +0000 (11:53 +0200)]
arm64: zynqmp: Add support for VPXA2785
VPXA2785(vp-x-a2785-00) is evaluation board which contains two PCIe-Edge
fingers, one for PCIe-B(gen5x8) and one for CPM(dual gen5x8, gen5x16).
Each of the ports can operate in endpoint or root port mode. This allows
the single card to be used for both root port, endpoint, and switch modes.
The board is designed in the similar manner as others Versal boards. It
means board also have ZynqMP Zu4 System Controller which is described in a
separate file.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/59d3b1f7e785bc65518b465e5122fd2787616a93.1695808407.git.michal.simek@amd.com
Michal Simek [Wed, 27 Sep 2023 09:53:34 +0000 (11:53 +0200)]
arm64: zynqmp: Describe i2c structures for SCs
Generic system controller (SC) covers connection defined by specification
but different boards have different i2c devices. That's why describe i2c
devices available on multiple boards.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ca1826b8b58981111229a94527818cc5a191ca9a.1695808407.git.michal.simek@amd.com
Michal Simek [Wed, 27 Sep 2023 09:53:33 +0000 (11:53 +0200)]
arm64: zynqmp: Add support for SC revC
System controller revC is using ADI ethernet phy instead of TI because of
supply chain issues.
Describe reset assert and de-assert times to 10us and 5ms respectively
according to the datasheet. Also setup RGMII RX and TX delay values to
2400ps as per board bring up observations.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2790f6cede7485556d581ab8270dda477fa21522.1695808407.git.michal.simek@amd.com
Michal Simek [Wed, 27 Sep 2023 09:53:32 +0000 (11:53 +0200)]
arm64: zynqmp: Create description for generic SC (vpk120-revB)
System controllers are pretty much the same on the all boards that's why
use autodetection based on i2c eeprom. This should end up with having only
one BSP for all SCs with only DT overlays to cover different i2c
structures.
All MIOs are fixed by the spec that's why not a problem to description
pinctrl setting.
Apart from eth phy reset, it also set proper phy delays.
The TI DP83867 PHY datasheet says:
T1: Post RESET stabilization time == 195us
T3: Hardware configuration pins transition to output drivers == 64us
T4: RESET pulse width == 1us
So with a little overhead set 'reset-assert-us' to 100us (T4) and
'reset-deassert-us' to 280us (T1+T3).
NOTE: The tuning of TI DP83867 phy reset delay is derived from linux
upstream commit:
5dbadc848259(arm64: dts: fsl: add support for Kontron
pitx-imx8m board).
i2c structure on Xilinx Versal evaluation platforms contain a lot of
devices but also connection to connectors like SFP. Because of this
complicated structure with also all level shifters, i2c muxes, etc. not all
devices are able to reliably work on 400kHz even if they are compatible
with this speed. That's why set i2c frequency to 100KHz to increase
reliability of the i2c bus.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c8092340f92144f0cc9096194198f227015bc013.1695808407.git.michal.simek@amd.com
Michal Simek [Wed, 27 Sep 2023 09:53:31 +0000 (11:53 +0200)]
arm64: zynqmp: Add support for vpk120-revA
Board contains two systems. The primary is Versal VP1202 ACAP device and
the secondary is ZynqMP zu4 which acts as system controller. The patch is
describing only ZynqMP system controller part.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/bd8b79d7c6693e90e12bce422f8ed00f2f43c9ae.1695808407.git.michal.simek@amd.com
Michal Simek [Wed, 27 Sep 2023 09:53:30 +0000 (11:53 +0200)]
arm64: zynqmp: Add x-prc-01/02/03/04/05 revA support from SC
Add i2c accessible devices with description.
There is versal specific eeprom and i2c-gpio controller.
SE3 has also clock chip present.
Also remove x-prc description from SC dts.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4f71ec6a63240fd4aaa3453824138281c50d71c3.1695808407.git.michal.simek@amd.com
Michal Simek [Wed, 27 Sep 2023 09:53:29 +0000 (11:53 +0200)]
arm64: zynqmp: Add support for vck190 revB system controller
There are some changes between revA and revB boards. u39 8T49N240 was
removed and also three ina226 at 42/43/44 addresses (u178/u180/u182).
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/461cfe5b2b882365413f90d19efd8abcd6be56ed.1695808407.git.michal.simek@amd.com
Michal Simek [Wed, 27 Sep 2023 09:53:28 +0000 (11:53 +0200)]
arm64: zynqmp: Remove xlnx,fclk nodes
xlnx,fclk nodes are not described in dtschema that's why remove them.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b25dedd066f587321751d7d20c1f65bb96c53b89.1695808407.git.michal.simek@amd.com
Michal Simek [Wed, 27 Sep 2023 09:53:27 +0000 (11:53 +0200)]
arm64: zynqmp: Add support for KD240 Kria SOM CC
Add support for KD240 Kria SOM CC. It is pretty much subset of KR260 board
from PS perspective.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/835f1d1b8982d46b902db69daad64e8445c051e9.1695808407.git.michal.simek@amd.com
Michal Simek [Fri, 22 Sep 2023 10:35:43 +0000 (12:35 +0200)]
arm64: zynqmp: Aligned QSPI configuration with latest spec
Official DT binding description for dual stacked/paralllel configurations
have been merged that's why switch to it.
Link: https://lore.kernel.org/r/20220126112608.955728-3-miquel.raynal@bootlin.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2912091c231f5e945ee44601c285fe16263448da.1695378830.git.michal.simek@amd.com
Michal Simek [Fri, 22 Sep 2023 10:35:42 +0000 (12:35 +0200)]
ARM: zynq: Describe nand device in DT
Linux requires to describe nand structure under nand controller.
If it is not described nand device is not detected by Linux.
Error shown by Linux kernel:
pl35x-nand-controller
e1000000.nand-controller: Incorrect number of NAND chips (0)
pl35x-nand-controller: probe of
e1000000.nand-controller failed with error -22
When wired:
nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xda
nand: Micron MT29F2G08ABAEAWP
nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3fcd68ccdfed5e6c079681e3b29e06583ec8a375.1695378830.git.michal.simek@amd.com
Michal Simek [Fri, 22 Sep 2023 10:35:41 +0000 (12:35 +0200)]
arm64: zynqmp: Sync licenses with Linux kernel
There is difference between licenses in the Linux kernel and there
shouldn't be any diff because all changes are coming from the same source
at the same time. The difference is really in a time when they were
upstreamed. That's why sync it up.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/813b29378083153b67c60772f28cd2613519f338.1695378830.git.michal.simek@amd.com
Michal Simek [Fri, 22 Sep 2023 10:35:40 +0000 (12:35 +0200)]
arm64: zynqmp: Convert kv260-revA overlay to ASCII text
File was in UTF-8 format but there is no reason for it. Convert it to
ASCII/plain text.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e4d52b898b461b86bb82009f37635f351279c753.1695378830.git.michal.simek@amd.com
Laurent Pinchart [Fri, 22 Sep 2023 10:35:39 +0000 (12:35 +0200)]
arm64: dts: zynqmp: Add ports for the DisplayPort subsystem
The DPSUB DT bindings now specify ports to model the connections with
the programmable logic and the DisplayPort output. Add them to the
device tree.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1c91420e90bc823d7529834c33438216857c7161.1695378830.git.michal.simek@amd.com
Laurent Pinchart [Fri, 22 Sep 2023 10:35:38 +0000 (12:35 +0200)]
arm64: dts: zynqmp: zcu106a: Describe DisplayPort connector
Add a device tree node to describe the DisplayPort connector, and
connect it to the DPSUB output.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fe037c93ed41bc5ca97887964037520d449ca98c.1695378830.git.michal.simek@amd.com
Michal Simek [Fri, 22 Sep 2023 10:35:37 +0000 (12:35 +0200)]
arm64: xilinx: Remove address/size-cells from gem nodes
Some boards are using one mdio bus which holds multiple phys and also
boards are using mdio node for bus description. That's why there are cases
where address/size-cells are unnecessary which is also reported by make W=1
dtbs. That's why remove them from zynqmp.dtsi and let board DTSes to handle
it based on used description.
Error log:
/axi/ethernet@
ff0e0000: unnecessary #address-cells/#size-cells without
"ranges" or child "reg" property
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/02f308c774d4f2a798a9a8c066824114a19841a7.1695378830.git.michal.simek@amd.com
Michal Simek [Fri, 22 Sep 2023 10:35:36 +0000 (12:35 +0200)]
arm64: xilinx: Put ethernet phys to mdio node
All zynqmp boards have been already described via mdio node that's why also
convert the rest of the boards. With using mdio node there is an option to
add reset property for the whole mdio bus which is reflected by
's/phy-reset-gpios/reset-gpios/g' for some boards.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ff165281a70a38e2b76fee91e6255ce95ce8021b.1695378830.git.michal.simek@amd.com
Michal Simek [Fri, 22 Sep 2023 10:35:35 +0000 (12:35 +0200)]
arm64: zynqmp: Fix Siva's email address format
Some patches didn't have his full name and also there was one more ">" at
the end of email address. That's why correct both of these issues.
Fixes: 174d728471d5 ("arm64: zynqmp: Switch to amd.com emails")
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e970cc0dfabe293c2baf6b231d34f3af0386f1eb.1695378830.git.michal.simek@amd.com
Michal Simek [Fri, 22 Sep 2023 10:35:34 +0000 (12:35 +0200)]
arm64: zynqmp: Describe bus-width for SD card on KV260
SD card is connected with 4 data lines which should be described properly.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/065cb9f1c6706eb4d70066e25cfc30d17b9f875d.1695378830.git.michal.simek@amd.com
Michal Simek [Fri, 22 Sep 2023 10:35:33 +0000 (12:35 +0200)]
arm64: xilinx: Use lower case for partition address
Lower case should be used for register address.
Issue is reported as:
flash@0: partitions: Unevaluated properties are not allowed
('partition@
22A0000' was unexpected)
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/66b3361df883ecab4f36ce3b4196fb606c802598.1695378830.git.michal.simek@amd.com
Michal Simek [Fri, 22 Sep 2023 10:35:32 +0000 (12:35 +0200)]
arm64: xilinx: Remove address/size-cells from flash node
Partitions are described via fixed-partitions that's why there is no need
to have address/size-cells in flash node.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c704be9d9f3d09c1cc55b092efeb9c73fcda6451.1695378830.git.michal.simek@amd.com
Tanmay Shah [Fri, 22 Sep 2023 10:35:31 +0000 (12:35 +0200)]
arm64: dts: xilinx: zynqmp: Add RPU subsystem device node
RPU subsystem can be configured in cluster-mode or split mode.
Also each r5 core has separate power domains.
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/dde364939b4fbe3f7be7b6f5dff42e7d8b2f5c46.1695378830.git.michal.simek@amd.com
Michal Simek [Fri, 22 Sep 2023 10:35:30 +0000 (12:35 +0200)]
arm64: zynqmp: Describe interrupts by using macros
Use arm-gic.h and irq.h for interrupt description. It helps to improve
readability of device tree file.
Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e0db567e1eb4e4e90e59270f41708919682dacf4.1695378830.git.michal.simek@amd.com
Michal Simek [Mon, 18 Sep 2023 14:11:23 +0000 (16:11 +0200)]
arm64: zynqmp: Remove resetin/out from K24 psu_init
The code is not called that's why remove it.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/7b207e90f68028ab36fcc22df4127492f174793d.1695046281.git.michal.simek@amd.com
Michal Simek [Mon, 18 Sep 2023 14:09:18 +0000 (16:09 +0200)]
arm64: zynqmp: Rename dt overlay file names from dts to dtso
Use dtso suffix instead of dts. Build option was introduced by
commit
a0f9a77912b2 ("kbuild: Allow DTB overlays to built from .dtso named
source files").
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1dce37e72428c14a3ccbb5dc674b90dfe56b75ac.1695046155.git.michal.simek@amd.com
Michal Simek [Mon, 18 Sep 2023 11:22:04 +0000 (13:22 +0200)]
arm64: zynqmp: Describe assigned-clocks for uarts
Describe assigned-clocks for both uarts. SOM is using this functionality.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/bddbb81209a4567b0939c5d2d0ecb42fdfcd71ea.1695036114.git.michal.simek@amd.com
Venkatesh Yadav Abbarapu [Thu, 14 Sep 2023 10:06:20 +0000 (15:36 +0530)]
pinctrl: zynqmp: Display the tristate configuration for all pins
Read the tristate config for all the pins and display it.
ZynqMP> pinmux status MIO1
MIO1: slew:fast bias:enabled pull:up input:cmos drive:12mA
volt:1.8 tri_state:enabled
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20230914100620.26346-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Venkatesh Yadav Abbarapu [Wed, 20 Sep 2023 03:00:06 +0000 (08:30 +0530)]
pinctrl: Increase size of pinmux status buffer
For Xilinx ZynqMP SOC new parameter was added and now it can
set 7 parameters for its pins. Pinmux status command will
print the status of these parameters for each pin. But
current print buffer length is only 80 characters long, increase it
to 90 to print all the parameters without truncation.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20230920030006.6488-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Venkatesh Yadav Abbarapu [Fri, 22 Sep 2023 04:50:10 +0000 (10:20 +0530)]
net: zynq_gem: Update the MDC clock divisor in the probe function
MDC clock change needs to be done when the driver probe function
is called as mdio is enabled at probe and not when the ethernet starts.
Setup the MDC clock at the probe itself.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20230922045010.22852-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Tom Rini [Fri, 6 Oct 2023 21:23:47 +0000 (17:23 -0400)]
Merge branch '2023-10-06-spl-prepare-for-universal-payload'
To quote the author:
This series tidies up SPL a little and adds some core ofnode functions
needed to support Universal Payload. It also includes a few minor
fix-ups for sandbox.
For SPL the changes include CONFIG naming, removing various #ifdefs and
tidying up the FIT code.
One notable piece of the ofnode improvements is support for flattening a
livetree. This should be useful in future as we move FDT fixups to use
the ofnode API.
Simon Glass [Tue, 26 Sep 2023 14:14:58 +0000 (08:14 -0600)]
pci: serial: Support reading PCI-register size with base
The PCI helpers read only the base address for a PCI region. In some cases
the size is needed as well, e.g. to pass along to a driver which needs to
know the size of its register area.
Update the functions to allow the size to be returned. For serial, record
the information and provided it with the serial_info() call.
A limitation still exists in that the size is not available when OF_LIVE
is enabled, so take account of that in the tests.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:57 +0000 (08:14 -0600)]
dm: core: Tweak device_is_on_pci_bus() for code size
This function cannot return true if PCI is not enabled, since no PCI
devices will have been bound. Add a check for this to reduce code size
where it is used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:56 +0000 (08:14 -0600)]
serial: Drop ns16550 serial_getinfo() in SPL
This is typically not needed in SPL/TPL and increases the code size.
Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:55 +0000 (08:14 -0600)]
spl: Add C-based runtime detection of SPL
The spl_phase() function indicates whether U-Boot is in SPL and before
or after relocation. But sometimes it is useful to check for SPL with
zero code-size impact. Since spl_phase() checks the global_data flags,
it does add a few bytes.
Add a new spl_in_proper() function to check if U-Boot proper is
running, regardless of the relocation status.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 27 Sep 2023 14:22:37 +0000 (08:22 -0600)]
command: Include a required header in command.h
This uses ARRAY_SIZE() but does not include the header file which declares
it. Fix this, so that command.h can be included without common.h
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Simon Glass [Tue, 26 Sep 2023 14:14:52 +0000 (08:14 -0600)]
bloblist: Add missing name
Add a missing bloblist name.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:51 +0000 (08:14 -0600)]
bloblist: Support initing from multiple places
Typically the bloblist is set up after the devicetree is present. This
makes sense because bloblist may use malloc() to allocate the space it
needs.
However sometimes the devicetree itself may be present in the bloblist.
In that case it is at a known location in memory so we can init the
bloblist very early, before devicetree.
Add a flag to indicate whether the bloblist has been inited. Add a
function to init it only if needed. Use that in the init sequence.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:50 +0000 (08:14 -0600)]
sandbox: Move the bloblist down a little in memory
Move this down by 4KB so that it is large enough to hold the devicetree.
Also fix up the devicetree address in the documetation while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:49 +0000 (08:14 -0600)]
sandbox: Only read the state if we have a state file
We should not read this unless requested. Make it conditional on the
option being provided.
Add some debugging to show the state being written.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:48 +0000 (08:14 -0600)]
sandbox: Init the EC properly even if no state file is available
This currently relies on sandbox attempting to read a state file. At
present it always does, even when there is no state file, in which case it
fails, but still inits the EC.
That is a bug, so update this driver to set the current image always, even
if no state is read.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:47 +0000 (08:14 -0600)]
sandbox: Move reading the RAM buffer into a better place
This should not happen in the argument-parsing function. Move it to the
main program.
Add some debugging for reading/writing.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:46 +0000 (08:14 -0600)]
dm: core: Add tests for oftree_path()
Add a few simple tests for getting the root node, since this is handled
as a special case in the implementation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:45 +0000 (08:14 -0600)]
dm: core: Support writing a 64-bit value
Add support for writing a single 64-bit value into a property.
Repurpose the existing tests to handle this case too.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:44 +0000 (08:14 -0600)]
dm: core: Support writing a boolean
Add functions to write a boolean property. This involves deleting it if
the value is false.
Add a new ofnode_has_property() as well. Add a comment about the behaviour
of of_read_property() when the property value is empty.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:43 +0000 (08:14 -0600)]
dm: core: Add a way to convert a devicetree to a dtb
Add a way to flatten a devicetree into binary form. For livetree this
involves generating the devicetree using fdt_property() and other calls.
For flattree it simply involves providing the buffer containing the tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:42 +0000 (08:14 -0600)]
dm: core: Add a way to delete a node
Add a function to delete a node in an existing tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:41 +0000 (08:14 -0600)]
dm: core: Add a way to copy a node
Add a function to copy a node to another place under a new name. This is
useful at least for testing, since copying a test node with existing
properties is easier than writing the code to generate it all afresh.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:40 +0000 (08:14 -0600)]
dm: core: Add a function to create an empty tree
Provide a function to create a new, empty tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:39 +0000 (08:14 -0600)]
dm: core: Tidy up comments in the ofnode tests
Add comments to the functions where the test name does not indicate what
is being tested. Rename functions in a few cases, so that a search for the
function will also file its test.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:38 +0000 (08:14 -0600)]
dm: core: Ensure we run flattree tests on ofnode
We need the UT_TESTF_SCAN_FDT flag set for these tests to run with flat
tree. In some cases it is missing, so add it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:37 +0000 (08:14 -0600)]
dm: core: Reverse the argument order in ofnode_copy_props()
Follow the order used by memcpy() as it may be less confusing.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:36 +0000 (08:14 -0600)]
spl: Move bloblist writing until the image is known
The bloblist should not be finalised until the image is fully set up.
This allows any final handoff information to be included in the bloblist.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:35 +0000 (08:14 -0600)]
spl: Use the correct FIT_..._PROP constants
Rather than open-coding the property names, use the existing constants
provided for this purpose. This better aligns the simple-FIT code with
the full FIT implementation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:34 +0000 (08:14 -0600)]
spl: Move the full FIT code to spl_fit.c
For some reason this code was put in the main spl.c file. Move it out
to the FIT implementation where it belongs.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:33 +0000 (08:14 -0600)]
spl: Rename spl_load_fit_image() to load_simple_fit()
We have two functions called spl_load_fit_image(), one in spl.c and one in
spl_fit.c
Rename the second one, to indicate that it relates to simple FIT parsing,
rather than the full version.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:32 +0000 (08:14 -0600)]
spl: Remove #ifdefs with BOOTSTAGE
This feature has some helpers in its header file so that its functions
resolve to nothing when the feature is disabled. Add a few more and use
these to simplify the code.
With this there are no more #ifdefs in board_init_r()
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:31 +0000 (08:14 -0600)]
spl: Avoid an #ifdef when printing gd->malloc_ptr
Use an accessor in the header file to avoid this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:30 +0000 (08:14 -0600)]
dm: core: Correct help in TPL_DM and VPL_DM
There are copying errors in the help. Fix these.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:29 +0000 (08:14 -0600)]
doc: Clean up SYS_MALLOC_SIMPLE
Move the useful help to Kconfig.
Drop mention of CONFIG_SYS_MALLOC_SIMPLE since it doesn't exist.
Correct a 'CONFIGSYS_MALLOC_F_LEN' typo
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:28 +0000 (08:14 -0600)]
Tidy up uses of CONFIG_SYS_MALLOC_F_LEN
Use CONFIG_SYS_MALLOC_F instead to of CONFIG_SYS_MALLOC_F_LEN to
determine whether pre-relocation malloc() is enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:27 +0000 (08:14 -0600)]
spl: Use SYS_MALLOC_F instead of SYS_MALLOC_F_LEN
Use the new SPL/TPL/VPL_SYS_MALLOC_F symbols to determine whether the
malloc pool exists.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
Simon Glass [Tue, 26 Sep 2023 14:14:26 +0000 (08:14 -0600)]
tpl: Enable CONFIG_TPL_SYS_MALLOC_F where needed
Enable CONFIG_TPL_SYS_MALLOC_F for boards which have a non-zero value
for CONFIG_TPL_SYS_MALLOC_F_LEN
Note that the default is yes in most cases, so no changes are needed to
board defconfig options.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:25 +0000 (08:14 -0600)]
spl: Enable CONFIG_SPL_SYS_MALLOC_F where needed
Enable CONFIG_SPL_SYS_MALLOC_F for boards which have a non-zero value
for CONFIG_SPL_SYS_MALLOC_F_LEN
Note that the default is yes in most cases, so no changes are needed to
board defconfig options.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:24 +0000 (08:14 -0600)]
spl: Create proper symbols for enabling the malloc() pool
For U-Boot proper we have CONFIG_SYS_MALLOC_F which indicates that a
malloc() pool is available before relocation.
For SPL we only have CONFIG_SPL_SYS_MALLOC_F_LEN which indicates the
size of the pool.
In various places we use CONFIG_SPL_SYS_MALLOC_F_LEN == 0 to indicate
that there is no pool.
This differing approach is confusing. Add a new CONFIG_SPL_SYS_MALLOC_F
symbol for SPL (and similarly for TPL and VPL). Tidy up the Kconfig
help for clarity.
For now these symbols are not used. That is cleaned up in the following
patches.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:23 +0000 (08:14 -0600)]
serial: Drop mention of SPL/TPL_SYS_MALLOC_F
These symbols do not (yet) exist, so drop the usage of them in the
serial Kconfig file. It has no effect.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:22 +0000 (08:14 -0600)]
spl: Drop the switch() statement for OS selection
This code is pretty ugly, with many #ifdefs
There are quite a lot of IH_OS_U_BOOT values so the compiler struggles
to create a jump table here. Also, most of the options are normally
disabled.
Change it to an else...if construct instead. Add an accessor for the
spl_image field behind an #ifdef to avoid needing #ifdef in the C code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:21 +0000 (08:14 -0600)]
spl: Avoid #ifdef with CONFIG_SPL_PAYLOAD_ARGS_ADDR
Move the condition to the header file to improve readability.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:20 +0000 (08:14 -0600)]
spl: Drop #ifdefs for BOARD_INIT and watchdog
Avoid using the preprocessor for these checks.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:19 +0000 (08:14 -0600)]
spl: mx6: powerpc: Drop the condition on timer_init()
It doesn't make sense to have some boards do this differently. Drop the
condition in the hope that the maintainers can figure out any run-time
problems.
This has been tested on qemu-ppce500
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Simon Glass [Tue, 26 Sep 2023 14:14:18 +0000 (08:14 -0600)]
spl: Avoid #ifdef with CONFIG_SPL_SYS_MALLOC
Use IF_ENABLED_INT() to avoid needing to use the preprocessor.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:17 +0000 (08:14 -0600)]
spl: Rename SYS_SPL_ARGS_ADDR to SPL_PAYLOAD_ARGS_ADDR
Rename this so that SPL is first, as per U-Boot convention. Also add
PAYLOAD_ since this is where in memory the parameters for the payload
have been stored.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Sep 2023 14:14:16 +0000 (08:14 -0600)]
spl: Use CONFIG_SPL... instead of CONFIG_..._SPL_...
We like to put the SPL first so it is clear that it relates to SPL. Rename
various malloc-related options which have crept in, to stick to this
convention.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Martyn Welch <martyn.welch@collabora.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
Tom Rini [Thu, 5 Oct 2023 17:26:44 +0000 (13:26 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
+ ae350: modify memory layout and target name
+ ae350: use generic RISC-V timer driver in S-mode
+ Support bootstage report for RISC-V
+ Support C extension exception command for RISC-V
+ Add Starfive timer support
Tom Rini [Thu, 5 Oct 2023 14:48:21 +0000 (10:48 -0400)]
Merge branch '2023-10-04-TI-dts-updates'
- Resync some TI K3 DTS files, to fix booting on them.
Tom Rini [Wed, 4 Oct 2023 22:49:58 +0000 (18:49 -0400)]
Merge tag 'dm-pull-4oct23' of https://source.denx.de/u-boot/custodians/u-boot-dm
moveconfig: enhance output; rename to qconfig
Neha Malcom Francis [Wed, 27 Sep 2023 13:09:56 +0000 (18:39 +0530)]
arm: dts: k3-j721e: Sync with v6.6-rc1
Sync k3-j721e DTS with kernel.org v6.6-rc1.
* Use mcu_timer0 defined in k3-j721e-mcu-wakeup.dtsi and remove
timer0, we have its clocks set up in clk-data now
* Remove hbmc node as support is buggy and needs to be fixed
* Remove aliases and chosen node, use them from Kernel
* Remove /delete-property/ and clock-frequency from sdhci,
usbss, and mcu_uart nodes as we have them in clk and dev data
* Remove dummy_clocks as they are not needed
* Remove cpsw node as it is not required since it has been fixed
in U-Boot
* Remove pcie nodes, they are not needed
* Remove mcu_i2c0 as it is used for tps659413 PMIC in j721e-sk
for which support is not yet added
* Change secproxy nodes to their Linux definitions
* Remove overriding of ti,cluster-mode in MAIN R5 to default to
lockstep mode same as Kernel
* Retain tps6594 node as TPS6594 PMIC support is still under
review in the Kernel [1], cleanup will be taken post its merge
[1] https://lore.kernel.org/all/
20230810-tps6594-v6-0-
2b2e2399e2ef@ti.com/
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Neha Malcom Francis [Wed, 27 Sep 2023 13:09:55 +0000 (18:39 +0530)]
arm: dts: k3-j721e-r5: Clean up inclusion hierarchy
Get rid of k3-j721e-r5-*-u-boot.dtsi as it is not
necessary. Change the inclusion hierarchy to be as follows:
k3-j721e-<board>.dts---
-
-->k3-j721e-r5-<board>.dts
-
k3-j721e-<board>-u-boot.dtsi---
Reason for explicitly mentioning the inclusion of -u-boot.dtsi in code
although it could've been automatically done by U-Boot is to resolve
some of the dependencies that R5 file requires.
Also remove duplicate phandles while making this shift as well as remove
firmware-loader as it serves no purpose without "phandlepart" property.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Neha Malcom Francis [Wed, 27 Sep 2023 13:09:54 +0000 (18:39 +0530)]
configs: j721e: Remove HBMC_AM654 config
Kernel commit
d93036b47f35 ("arm64: dts: ti: k3-j721e-mcu_wakeup: Add
HyperBus node") was merged to kernel without its dependent patch [1].
Similar fix is needed in U-Boot, and hbmc currently breaks boot. Till
this gets fixed in U-Boot, disable the config by default so that the
hbmc probe that happens in board/ti/j721e/evm.c will not take place
and lead to boot failure.
[1] https://lore.kernel.org/all/
20230424184810.29453-1-afd@ti.com/
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Neha Malcom Francis [Wed, 27 Sep 2023 13:09:53 +0000 (18:39 +0530)]
drivers: firmware: ti_sci: Get SCI revision only if TIFS/SYSFW is up
When setting up boot media to load the TIFS binary in legacy boot flow
(followed by J721E), get_timer() is called which calls dm_timer_init()
which then gets the tick-timer: mcu_timer0. mcu_timer0 uses k3_clks
(clock controller) and k3_pds (power controller) from the dmsc node that
forces probe of the ti_sci driver of TIFS that hasn't been loaded yet!
Running ti_sci_cmd_get_revision from the probe leads to panic since no
TIFS and board config binaries have been loaded yet. Resolve this by
moving ti_sci_cmd_get_revision to ti_sci_get_handle_from_sysfw as a
common point of invocation for both legacy and combined boot flows.
Before doing this, it is important to go through whether any sync points
exist where revision is needed before ti_sci_get_handle_from_sysfw is
invoked. Going through the code along with boot tests on both flows
ensures that there are none.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Neha Malcom Francis [Wed, 27 Sep 2023 13:09:52 +0000 (18:39 +0530)]
arm: mach-k3: j721e_init: Move clk_k3 probe before loading TIFS
When setting boot media to load the TIFS binary in legacy boot flow
(followed by J721E), get_timer() is called which eventually calls
dm_timer_init() to grab the tick-timer, which is mcu_timer0. Since we
need to set up the clocks before using the timer, move clk_k3 driver
probe before k3_sysfw_loader to ensure we have all necessary clocks set
up before.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Neha Malcom Francis [Wed, 27 Sep 2023 13:09:51 +0000 (18:39 +0530)]
arm: mach-k3: j721e: dev-data: Add mcu_timer0 ID
U-Boot uses mcu_timer0 as the tick-timer, so add it to device list.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Nishanth Menon [Mon, 2 Oct 2023 15:00:53 +0000 (10:00 -0500)]
arm: dts: k3-am625-beagleplay: Fix Boot
Since commit [1] A53 u-boot proper is broken. This is because nodes
marked as 'bootph-pre-ram' are not available at u-boot proper before
relocation.
To fix this we mark all nodes in u-boot.dtsi as 'bootph-all'.
[1]
9e644284ab812 ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation")
Reported-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Roger Quadros [Fri, 29 Sep 2023 13:46:46 +0000 (16:46 +0300)]
arm: dts: k3-am625-sk: Mark dependent nodes for pre-relocation phase
CPSW node needs PHY, MDIO, pinmux, DMA and INTC nodes.
main_conf is required for phy_gmii_sel.
Mark them as 'bootph-all' so they are available in all
pre-relocation phases.
Fixes the below dts warnings:
<stdout>: Warning (reg_format): /bus@f0000/syscon@100000/phy@4044:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1)
<stdout>: Warning (reg_format): /bus@f0000/ethernet@
8000000/ethernet-ports/port@1:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
<stdout>: Warning (unit_address_vs_reg): /bus@f0000/syscon@100000: node has a unit name, but no reg or ranges property
<stdout>: Warning (pci_device_reg): Failed prerequisite 'reg_format'
<stdout>: Warning (pci_device_bus_num): Failed prerequisite 'reg_format'
<stdout>: Warning (simple_bus_reg): Failed prerequisite 'reg_format'
<stdout>: Warning (i2c_bus_reg): Failed prerequisite 'reg_format'
<stdout>: Warning (spi_bus_reg): Failed prerequisite 'reg_format'
<stdout>: Warning (avoid_default_addr_size): /bus@f0000/syscon@100000/phy@4044: Relying on default #address-cells value
<stdout>: Warning (avoid_default_addr_size): /bus@f0000/syscon@100000/phy@4044: Relying on default #size-cells value
<stdout>: Warning (avoid_default_addr_size): /bus@f0000/ethernet@
8000000/ethernet-ports/port@1: Relying on default #address-cells value
<stdout>: Warning (avoid_default_addr_size): /bus@f0000/ethernet@
8000000/ethernet-ports/port@1: Relying on default #size-cells value
<stdout>: Warning (avoid_unnecessary_addr_size): Failed prerequisite 'avoid_default_addr_size'
<stdout>: Warning (unique_unit_address): Failed prerequisite 'avoid_default_addr_size'
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Roger Quadros [Fri, 29 Sep 2023 13:46:45 +0000 (16:46 +0300)]
arm: dts: k3-am625-sk: Fix boot
Since commit [1] A53 u-boot proper is broken.
This is because nodes marked as 'bootph-pre-ram' are
not available at u-boot proper before relocation.
To fix this we mark all nodes in sk-u-boot.dtsi as
'bootph-all'.
[1]
9e644284ab812 ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Roger Quadros [Fri, 29 Sep 2023 13:46:44 +0000 (16:46 +0300)]
arm: dts: k3-am642-sk: Mark dependent nodes for pre-relocation phase
CPSW node needs PHY, MDIO, pinmux, DMA and INTC nodes.
Mark them as 'bootph-all' so they are available in all
pre-relocation phases.
Fixes below dts warnings:
<stdout>: Warning (reg_format): /bus@f4000/ethernet@
8000000/mdio@f00/ethernet-phy@1:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
<stdout>: Warning (unit_address_vs_reg): /bus@f4000/ethernet@
8000000/mdio@f00: node has a unit name, but no reg or ranges property
<stdout>: Warning (pci_device_reg): Failed prerequisite 'reg_format'
<stdout>: Warning (pci_device_bus_num): Failed prerequisite 'reg_format'
<stdout>: Warning (simple_bus_reg): Failed prerequisite 'reg_format'
<stdout>: Warning (i2c_bus_reg): Failed prerequisite 'reg_format'
<stdout>: Warning (spi_bus_reg): Failed prerequisite 'reg_format'
<stdout>: Warning (avoid_default_addr_size): /bus@f4000/ethernet@
8000000/mdio@f00/ethernet-phy@1: Relying on default #address-cells value
<stdout>: Warning (avoid_default_addr_size): /bus@f4000/ethernet@
8000000/mdio@f00/ethernet-phy@1: Relying on default #size-cells value
<stdout>: Warning (avoid_unnecessary_addr_size): Failed prerequisite 'avoid_default_addr_size'
<stdout>: Warning (unique_unit_address): Failed prerequisite 'avoid_default_addr_size'
<stdout>: Warning (msi_parent_property): /bus@f4000/bus@
48000000/dma-controller@
485c0100:msi-parent: Could not get phandle node for (cell 0)
<stdout>: Warning (msi_parent_property): /bus@f4000/bus@
48000000/dma-controller@
485c0000:msi-parent: Could not get phandle node for (cell 0)
<stdout>: Warning (phys_property): /bus@f4000/ethernet@
8000000/ethernet-ports/port@2:phys: Could not get phandle node for (cell 0)
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Roger Quadros [Fri, 29 Sep 2023 13:46:43 +0000 (16:46 +0300)]
arm: dts: k3-am642-sk: Fix boot
Since commit [1] A53 u-boot proper is broken.
This is because nodes marked as 'bootph-pre-ram' are
not available at u-boot proper before relocation.
To fix this we mark all nodes in sk-u-boot.dtsi as
'bootph-all'.
Move cbass_mcu node to -r5-sk.dts as it is only required
for R5 SPL.
[1]
9e644284ab812 ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Roger Quadros [Fri, 29 Sep 2023 13:46:42 +0000 (16:46 +0300)]
arm: dts: k3-am64-evm: Mark dependent nodes for pre-relocation phase
CPSW node needs PHY, MDIO, pinmux, DMA and INTC nodes.
USB and MMC nodes need pinmux.
Mark them as 'bootph-all' so they are available in all
pre-relocation phases.
Fixes below dts warning:
<stdout>: Warning (dmas_property): /bus@f4000/ethernet@
8000000:dmas: Could not get phandle node for (cell 0)
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Roger Quadros [Fri, 29 Sep 2023 13:46:41 +0000 (16:46 +0300)]
arm: dts: k3-am64-evm: Fix boot
Since commit [1] A53 u-boot proper is broken.
This is because nodes marked as 'bootph-pre-ram' are
not available at u-boot proper before relocation.
To fix this we mark all nodes in sk-u-boot.dtsi as
'bootph-all'.
Move vtt_supply and cbass_mcu node to -r5-evm.dts as
it is only required for R5 SPL.
[1]
9e644284ab812 ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Simon Glass [Sat, 23 Sep 2023 19:44:16 +0000 (13:44 -0600)]
qconfig: Update the documentation
Update qconfig's documentation to better reflect its new purpose in life.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 23 Sep 2023 19:44:15 +0000 (13:44 -0600)]
qconfig: Rename the database file
Use qconfig.db as the new name, to reflect the tool's purpose.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 23 Sep 2023 19:44:14 +0000 (13:44 -0600)]
moveconfig: Rename the tool to qconfig
This does not move configs anymore, but queries them, based on a database
it can build. Rename the tool to better reflect its purpose.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 23 Sep 2023 19:44:13 +0000 (13:44 -0600)]
moveconfig: Move summaries to the end
Write the summary for -s and -b at the end, using a unified format.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 23 Sep 2023 19:44:12 +0000 (13:44 -0600)]
moveconfig: Drop the initial output
Since moveconfig now just does what it is told (build database or sync
defconfigs) we don't need to print what it is doing. Drop this info, which
is of very little use.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 23 Sep 2023 19:44:11 +0000 (13:44 -0600)]
moveconfig: Show a summary at the end
Rather than printing all the failed boards, which are now easily visible
on the terminal, just show a summary. Sort it by defconfig and drop the
'_defconfig' suffix.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 23 Sep 2023 19:44:10 +0000 (13:44 -0600)]
moveconfig: Show failures in progress
Show the number of accumulated failures when processing. Use a shorter
format with colour.
An unwanted space appears before the defconfig name on every item except
the last. Fix that while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 23 Sep 2023 19:44:09 +0000 (13:44 -0600)]
moveconfig: Use u_boot_pylib for terminal colour
Use the existing terminal code to handle ANSI colours. Enable colour by
default if the output is going to a terminal.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 23 Sep 2023 19:44:08 +0000 (13:44 -0600)]
moveconfig: Avoid showing progress at the end
When the process is finished, moveconfig leaves a line saying that all
boards were processed (for better or worse). Drop this, since it is
unncessary.
Future work will provide a summary at the end instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 23 Sep 2023 19:44:07 +0000 (13:44 -0600)]
moveconfig: Reduce the amount of output
Output a single line in the case where the defconfig only has one line
of output. Show the name without the _defconfig suffix, since that is the
same for all boards.
Use a list for the log so it is easier to process at the end.
Signed-off-by: Simon Glass <sjg@chromium.org>