Kever Yang [Fri, 15 Nov 2019 03:04:37 +0000 (11:04 +0800)]
ram: rockchip: add common code for sdram driver
There are some function like os_reg setting, capacity detect functions,
can be used as common code for different Rockchip SoCs, add a
sdram_common.c for all these functions.
Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 15 Nov 2019 03:04:35 +0000 (11:04 +0800)]
rockchip: sdram: extend to use sys_reg3 for capacity info
Since we have new DRAM type and to support different DRAM size in different
CS, we need more bits, so introduce sys_reg3 to record the info.
Note that the info in sys_reg3 is extension to sys_reg2 and the info in
sys_reg2 is the same as before. We define the DRAM_INFO with sys_reg3 as
VERSION2.
All the ENC macro are moved to sdram_common.h since the sdram.c only
need to do the info decode.
Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 15 Nov 2019 03:04:34 +0000 (11:04 +0800)]
rockchip: sdram: move cap structure and debug function to sdram_common.h
The sdram.h suppose to be helper file for sdram.c which including dram
size decode and some u-boot related dram init interface, and all
structure and function for dram driver move to sdram_common.h
Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 15 Nov 2019 03:04:33 +0000 (11:04 +0800)]
ram: rockchip: rename sdram_common.c/h to sdram.c
rename sdram_common.c in arch/arm/mach-rockchip to sdram.c;
so that we can use the file name sdram_common.c in dram driver for
better understand the code;
clean the related file who has use the header file at the same time.
Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
- Migrate the symbol CONFIG_SYS_REDUNDAND_ENVIRONMENT to Kconfig. This
is size neutral outside of two platforms with latent bugs being fixed
now and they no longer have "ENV_IS_NOWHERE" set along with their
intended location.
With recent update in u-boot gitattributes all files are treated as regular
text files. This creates problems with special files and repo always
shows uncommitted files like below.
Your branch is up-to-date with 'origin/master'.
Changes not staged for commit:
(use "git add <file>..." to update what will be committed)
(use "git checkout -- <file>..." to discard changes in working directory)
Simon Glass [Thu, 7 Nov 2019 00:22:44 +0000 (17:22 -0700)]
binman: tegra: Adjust symbol calculation depending on end-at-4gb
A recent change adjusted the symbol calculation to work on x86 but broke
it for Tegra. In fact this is because they have different needs.
On x86 devices the code is linked to a ROM address and the end-at-4gb
property is used for the image. In this case there is no need to add the
base address of the image, since the base address is already built into
the offset and image-pos properties.
On other devices we must add the base address since the offsets start at
zero.
In addition the base address is currently added to the 'offset' and 'size'
values. It should in fact only be added to 'image-pos', since 'offset' is
relative to its parent and 'size' is not actually an address. This code
should have been adjusted when support for 'image-pos' and 'size' was
added, but it was not.
To correct these problems:
- move the code that handles adding the base address to section.py, which
can check the end-at-4gb property and which property
(offset/size/image-pos) is being read
- add the base address only when needed (only for image-pos and not if the
image uses end-at-4gb)
- add a note to the documentation
- add a separate test to cover x86 behaviour
Fixes: 15c981cc (binman: Correct symbol calculation with non-zero image base) Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
Tom Rini [Mon, 11 Nov 2019 19:19:32 +0000 (14:19 -0500)]
Merge tag 'u-boot-rockchip-20191110' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Add support for rockchip pmic rk805,rk809, rk816, rk817
- Add rk3399 board Leez support
- Fix bug in rk3328 ram driver
- Adapt SPL to support ATF bl31 with entry at 0x40000
- Fix the u8 type comparision with '-1'.
- Fix checkpatch warning for multi blank line and review signature.
Levin Du [Thu, 17 Oct 2019 07:22:38 +0000 (15:22 +0800)]
rockchip: adding the missing "/" in entries of boot_devices
Without the prefix, "same-as-spl" in `u-boot,spl-boot-order` will not work
as expected. When board_boot_order() `spl-boot-order.c` meets
"same-as-spl", it gets the conf by looking the boot_devices table by boot
source, and parse the node by the conf with:
node = fdt_path_offset(blob, conf);
which will failed without the "/" indicating the path.
Currently only entries of boot_devices in rk3399 have the "/" prefix.
Therefore add the missing ones in other boards.
Signed-off-by: Levin Du <djw@t-chip.com.cn> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 18 Oct 2019 07:54:16 +0000 (15:54 +0800)]
rockchip: config: update CONFIG_SPL_MAX_SIZE for 64bit CPUs
Since we move the ATF bl31 entry for 64bit CPUs to 0x40000, we need to
limit the SPL size in 0x40000(start from 0) so that we don't need to do
the relocate for ATF loading.
Note that there will be separate BSS, STACK and MALLOC heap, so the size
0x40000(256KB) should be enough for SPL text.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 18 Oct 2019 07:54:15 +0000 (15:54 +0800)]
rockchip: rk3399: update SPL_STACK_R_ADDR
Use the same SPL_STACK_R_ADDR in Kconfig instead of each board config;
default to 0x4000000(64MB) instead of 0x80000(512KB) for this address
can support all the SoCs including those may have only 64MB memory, and
also reserve enough space for atf, kernel(in falcon mode) loading.
After the ATF entry move to 0x40000, the stack from 0x80000 may be override
when loading ATF bl31.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Wed, 23 Oct 2019 03:10:36 +0000 (11:10 +0800)]
rockchip: evb-px5: defconfig: no need to reserve IRAM for SPL
We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code,
and when we introduce the TPL, the SPL space is in DRAM, we reserve
space to avoid SPL text overlap with ATF bl31.
Now we decide to move ATF entry point to 0x40000 instead of 0x1000,
so that the SPL can have 0x4000 as code size and no need to reserve
space or relocate before loading ATF.
The mainline ATF has update since: 0aad563c rockchip: Update BL31_BASE to 0x40000
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Wed, 23 Oct 2019 02:08:53 +0000 (10:08 +0800)]
rockchip: rk3328: defconfig: no need to reserve IRAM for SPL
We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code,
and when we introduce the TPL, the SPL space is in DRAM, we reserve
space to avoid SPL text overlap with ATF bl31.
Now we decide to move ATF entry point to 0x40000 instead of 0x1000,
so that the SPL can have 0x4000 as code size and no need to reserve
space or relocate before loading ATF.
The mainline ATF has update since: 0aad563c rockchip: Update BL31_BASE to 0x40000
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 18 Oct 2019 07:54:14 +0000 (15:54 +0800)]
rockchip: rk3399: defconfig: no need to reserve IRAM for SPL
We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code,
and when we introduce the TPL, the SPL space is in DRAM, we reserve
space to avoid SPL text overlap with ATF bl31.
Now we decide to move ATF entry point to 0x40000 instead of 0x1000,
so that the SPL can have 0x4000 as code size and no need to reserve
space or relocate before loading ATF.
The mainline ATF has update since: 0aad563c rockchip: Update BL31_BASE to 0x40000
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Joseph Chen [Sun, 6 Oct 2019 18:10:22 +0000 (20:10 +0200)]
common: spl: atf: support booting bl32 image
Trusted-Firmware can also initialize a secure payload to use as a trusted
execution environment. In general for the arm64 case this is provided as
separate image and uboot is supposed to also place it in a predetermined
location in memory and add the necessary parameters to the ATF boot params.
So add the possibility to get this tee payload from the provided FIT image
and setup things as necessary.
Tested on a Rockchip PX30 with mainline TF-A, mainline OP-Tee (with pending
PX30 support) and mainline 5.4-rc1 Linux kernel.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Sun, 6 Oct 2019 18:10:21 +0000 (20:10 +0200)]
rockchip: make_fit_atf.py: allow inclusion of a tee binary
A trusted execution environment should also get loaded as loadable from
a fit image, so add the possibility to present a tee.elf to make_fit_atf.py
that then gets included as additional loadable into the generated its.
For ease of integration the additional loadable is created as atf_(x+1)
after all others to re-use core generation loops.
Tested against the combinations of 1-part-atf and multi-part-atf each
time with and without a tee binary present.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Simon South [Sun, 6 Oct 2019 16:28:13 +0000 (12:28 -0400)]
ram: rk3328: Use correct frequency units in function
Fix a pair of tests in phy_dll_bypass_set() that used incorrect units
for the DDR frequency, causing the DRAM controller to be misconfigured
in most cases.
Signed-off-by: Simon South <simon@simonsouth.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Emmanuel Vadot [Tue, 8 Oct 2019 17:59:50 +0000 (19:59 +0200)]
rockchip: dts: rk3328: rock64: Add same-as-spl order
rk3328 can use same-as-spl option so next loaders are loaded from the same
medium.
Add the boot order in the rock64 dts otherwise booting from sdcard
will result in u-boot looking into the eMMC.
Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Tested-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andy Yan [Sun, 22 Sep 2019 10:06:56 +0000 (18:06 +0800)]
rockchip: rk3399: Add Leez P710 support
Specification
- Rockchip RK3399
- LPDDR4
- TF sd scard slot
- eMMC
- M.2 B-Key for 4G LTE
- AP6256 for WiFi + BT
- Gigabit ethernet
- HDMI out
- 40 pin header
- USB 2.0 x 2
- USB 3.0 x 1
- USB 3.0 Type-C x 1
- TYPE-C Power supply
Commit details of rk3399-leez-p710.dts sync from linus tree for Linux 5.4-rc1:
"arm64: dts: rockchip: Add dts for Leez RK3399 P710 SBC"
(sha1: fc702ed49a8668a17343811ee28214d845bfc5e6)
Signed-off-by: Andy Yan <andyshrk@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Joseph Chen [Thu, 26 Sep 2019 07:45:07 +0000 (15:45 +0800)]
power: pmic: rk809: support rk809 pmic
The RK809 is a Power Management IC (PMIC) for multimedia
and handheld devices. They contains the following components:
- Regulators(5*BUCKs, 9*LDOs, 2*SWITCHes)
- RTC
- Clocking
Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Joseph Chen [Thu, 26 Sep 2019 07:44:55 +0000 (15:44 +0800)]
power: pmic: rk817: support rk817 pmic
The RK817 is a Power Management IC (PMIC) for multimedia
and handheld devices. They contains the following components:
- Regulators(4*BUCKs, 1* BOOST, 9*LDOs, 1*SWITCH)
- RTC
- Clocking
Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The RK805 are a Power Management IC (PMIC) for multimedia
and handheld devices. They contains the following components:
- Regulators(4*BUCKs, 3*LDOs)
- RTC
- Clocking
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The RK816 is a Power Management IC (PMIC) for multimedia
and handheld devices. They contains the following components:
- Regulators(4*BUCKs, 1*BOOST, 6*LDOs, 1*SWITCH)
- RTC
- Clocking
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
power: regulator: rk8xx: update the driver for rk808 and rk818
In order to adapt the following pmics, make the interface more compatible.
Support buck and ldo suspend voltage setting and getting.
Supprot buck and ldo suspend enable/disable setting and getting.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tom Rini [Fri, 8 Nov 2019 14:26:18 +0000 (09:26 -0500)]
tools/img2brec.sh: Delete unused tool
This script was only used on the MX1ADS board (and possibly other MX1
platforms) to program the flash. As we no longer have any boards for
that SoC, remove this tool.
Fixes: e570aca9474b ("mx1ads: remove board support") Signed-off-by: Tom Rini <trini@konsulko.com>
AKASHI Takahiro [Fri, 8 Nov 2019 01:32:15 +0000 (10:32 +0900)]
cmd: move down CONFIG_CMD_BOOTEFI after CONFIG_BOOTM_VXWORKS
Due to the commit 4b0bcfa7c4ec ("Kconfig: Migrate CONFIG_BOOTM_* options")
BOOTEFI and BOOTEFI_HELLO_COMPILE (and other BOOTEFI configs) are
displayed in a long distance. This will make it difficult for us to
understand that those configurations are closely related.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
Pankaj Bansal [Thu, 31 Oct 2019 05:41:09 +0000 (05:41 +0000)]
fsl-layerscape: fix warning if no hwconfig is defined
While getting the 'subarg' of 'hwconfig' env variable in
config_core_prefetch(), if no hwconfig variable is defined,
below warning is received:
WARNING: Calling __hwconfig without a buffer and
before environment is ready
Fix this by checking 'hwconfig' env variable.
If not found return without further processing.
Michael Walle [Sat, 26 Oct 2019 00:39:12 +0000 (02:39 +0200)]
drivers: net: fsl_enetc: fix RGMII configuration
Add the missing RGMII PHY modes in which case the MAC has configure its
RGMII settings. The only difference between these modes is the RX and
TX delay configuration. A user might choose any RGMII mode in the device
tree.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The fsl-layerscape already occupies board_late_init(), therefore it is
not possible for a board to have its own board_late_init(). Introduce
fsl_board_late_init() which can be implemented in the board specific
code.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 21 Oct 2019 23:10:57 +0000 (01:10 +0200)]
armv8: fsl-lsch3: convert CONFIG_TARGET_x to CONFIG_ARCH_x
The clocks are not dependent on the target but only on the SoC.
Therefore, convert the CONFIG_TARGET_x macros to the corresponding
CONFIG_ARCH_x. This will allow other targets to automatically use the
common code. Otherwise every new target would have to add itself to the
"#if defined(CONFIG_TARGET_x) || .." macros.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Laurentiu Tudor [Fri, 18 Oct 2019 09:01:56 +0000 (09:01 +0000)]
armv8: ls1028a: add erratum A-050382 workaround
Erratum A-050382 states that the eDMA ICID programmed in the eDMA_AMQR
register in DCFG is not correctly forwarded to the SMMU.
The workaround consists in programming the eDMA ICID in the eDMA_AMQR
register in DCFG to 40.
Laurentiu Tudor [Fri, 18 Oct 2019 09:01:53 +0000 (09:01 +0000)]
fsl-layerscape: fix compile error with sec fw disabled
If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n), below
compilation error appears
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h:169:4: error:
'CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT' undeclared here (not in a function)
Mathew McBride [Fri, 18 Oct 2019 03:27:53 +0000 (14:27 +1100)]
armv8: dts: ls1088a: add PSCI binding for LS1088A
This allows the use of PSCI calls to trusted firmware to
initiate reset and poweroff events with CONFIG_PSCI_RESET and
CONFIG_ARM_PSCI_FW. This is desirable, for example, if the target
board has implemented a custom reset or poweroff procedure in EL3.
Pankaj Bansal [Mon, 14 Oct 2019 11:43:19 +0000 (11:43 +0000)]
pci: layerscape: Only set EP CFG READY bit
In ls_pcie_ep_enable_cfg(), as part of EP setup,config ready bit
of pci controller is set, so that RC can read the config space of EP.
While setting the config ready bit, LTSSM_EN bit in same register was
also inadvertently getting cleared. This restarts the link training
between RC and EP.
Update code to just set the desired CFG_READY bit (bit 0),
while leaving the other bits unchanged.
Andrew F. Davis [Thu, 7 Nov 2019 13:06:09 +0000 (08:06 -0500)]
configs: j721e_evm_r5_defconfig: Remove SPL multi-DTB FIT support
The SPL FIT will only have one DTB, so remove support for multi-DTB. This
also removes an early access to EEPROM used to select the DTB that is not
valid in SPL at the point at which it is accessed, that always returns
false for GP devices and causes a firewall expection on HS.
Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Adam Ford [Mon, 4 Nov 2019 23:05:24 +0000 (17:05 -0600)]
Kconfig: ti: Make board detect EEPROM addresses depend BOARD_DETECT
There is an option to enable the board detection for TI platforms.
If this is option is not set, there is no reason to set the EEPROM
bus address or chip address.
This patch makes both EEPROM_BUS_ADDRESS and EEPROM_CHIP_ADDRESS
depend on TI_I2C_BOARD_DETECT.
Add VTM node for voltage and thermal management. For u-boot, this is needed
for supporting AVS class 0, as the efuse values for the OPPs are stored
under the VTM.
Tero Kristo [Thu, 24 Oct 2019 09:30:57 +0000 (15:00 +0530)]
arm: dts: k3-am654-r5-base-board: enable wkup_vtm0 node and link in supplies
Link the vdd-supplies for the voltage domains under the VTM node. Also,
enable the node under SPL. This will enable the AVS class 0 support on
am65x-evm board.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
Tero Kristo [Thu, 24 Oct 2019 09:30:56 +0000 (15:00 +0530)]
arm: dts: k3-am654-r5-base-board: add supply rail for MPU
MPU voltage on AM65x-evm is controlled via the TPS62363 chip attached
to i2c0 bus. Add device node for this so that it can be controlled via
a regulator driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
Keerthy [Thu, 24 Oct 2019 09:30:54 +0000 (15:00 +0530)]
arm: dts: k3-am654-r5-base-board: Add VTM node
Add VTM node for voltage and thermal management. For u-boot, this is needed
for supporting AVS class 0, as the efuse values for the OPPs are stored
under the VTM.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
Tero Kristo [Thu, 24 Oct 2019 09:30:48 +0000 (15:00 +0530)]
power: regulator: tps6236x: add support for tps6236x regulators
TPS6236x is a family of step down DC-DC converters optimized for battery
powered portable applications for a small solution size. Add a regulator
driver for supporting these devices.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
Tero Kristo [Thu, 24 Oct 2019 09:30:46 +0000 (15:00 +0530)]
misc: k3_avs: add driver for K3 Adaptive Voltage Scaling Class 0
Adaptive Voltage Scaling is a technology used in TI SoCs to optimize
the operating voltage based on characterization data written to efuse
during production. Add a driver to support this feature for K3 line of
SoCs, initially for AM65x.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
liu hao [Thu, 31 Oct 2019 07:51:08 +0000 (07:51 +0000)]
arm: add initial support for the Phytium Durian Board
This adds platform code and the device tree for the Phytium Durian Board.
The initial support comprises the UART and the PCIE.
Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Tom Rini <trini@konsulko.com> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Steven Hao <liuhao@phytium.com.cn>
Alexander Dahl [Wed, 30 Oct 2019 15:53:55 +0000 (16:53 +0100)]
cmd: mtdparts: Fix build with option ..._SHOW_NET_SIZES
That option is currently not used by any defconfig and could not be set
anymore since it became mandatory to used Kconfig when introducing new
options with U-Boot v2016.11 or commit eed921d92348 ("Kconfig: Add a
whitelist of ad-hoc CONFIG options") and commit 371244cb19f9 ("Makefile:
Give a build error if ad-hoc CONFIG options are added").
It was also not considered when fixing build warnings in
commit 39ac34473f3c ("cmd_mtdparts: use 64 bits for flash size,
partition size & offset") and could probably not be compiled anyway
after commit dfe64e2c8973 ("mtd: resync with Linux-3.7.1"), which
renamed some members of struct mtd_info … so it was probably broken
since then, which was U-Boot v2013.07-rc1.
However it still seems to work, see example output below:
Alexander Dahl [Wed, 30 Oct 2019 15:53:54 +0000 (16:53 +0100)]
cmd: nand: Remove not used declaration
This declaration is not used anywhere in the whole tree. There is a
function 'mtd_id_parse()' which was renamed from 'id_parse()' in
commit 68d7d65100e8 ("Separate mtdparts command from jffs2"), but that
function is not used (anymore?) in cmd nand and build is fine without
that declaration, so it's probably just safe to remove.
In file included from ../common/cli_hush.c:79:
../include/malloc.h:364:7: error: conflicting types for ‘memset’
void* memset(void*, int, size_t);
^~~~~~
In file included from ../include/compiler.h:126,
from ../include/env.h:12,
from ../common/cli_hush.c:78:
../include/linux/string.h:103:15:
note: previous declaration of ‘memset’ was here
extern void * memset(void *,int,__kernel_size_t);
^~~~~~
In file included from ../common/cli_hush.c:79:
../include/malloc.h:365:7: error: conflicting types for ‘memcpy’
void* memcpy(void*, const void*, size_t);
^~~~~~
In file included from ../include/compiler.h:126,
from ../include/env.h:12,
from ../common/cli_hush.c:78:
../include/linux/string.h:106:15:
note: previous declaration of ‘memcpy’ was here
extern void * memcpy(void *,const void *,__kernel_size_t);
^~~~~~
According to the U-Boot coding style guide common.h should be the first
include.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
When full malloc is enabled and SYS_MALLOC_F is also enabled, the simple
pre-reloc heap is used before relocation. In this case, calloc() uses
the MALLOC_ZERO macro to zero out the allocated memory. However, since
this macro is specially crafted for the dlmalloc implementation, it
does not always work for simple malloc.
For example, when allocating 16 bytes via simple malloc, only the first
12 bytes get zeroed out. The last 4 bytes will remain untouched.
This is a problem for DM drivers that are allocated before relocation:
memory allocated via 'platdata_auto_alloc_size' might not be set to
zero, resulting in bogus behaviour.
To fix this, use 'memset' instead of 'MALLOC_ZERO' to zero out memory
that compes from simple malloc.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Some U-Boot pointers have redundant information, so we can use a scheme
where we can return either an error code or a pointer with the same
return value. The default implementation just casts the pointer to a
number, however, this may fail on platforms where the end of the address
range is used for valid pointers (e.g. 0xffffff00 is a valid heap pointer
in socfpga SPL). For such platforms, this value provides an upper range
of those error pointer values - up to 'MAX_ERRNO' bytes below this value
must be unused/invalid addresses.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
projects / u-boot.git / log
