Michael Walle [Wed, 13 Oct 2021 16:14:03 +0000 (18:14 +0200)]
arm: dts: ls1028a: add an empty /soc
To keep the device tree similar to the linux kernel one, we need to move
all CCSR related devices into the /soc node. To keep the patches easy to
review, we initially add an empty /soc node and populate it piece by
piece.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Wed, 13 Oct 2021 16:14:01 +0000 (18:14 +0200)]
arm: dts: ls1028a: remove /memory node
This node is some hodgepodge between the ddr controller node at SoC
offset 0x1080000 and some static memory size of 2GiB. Remove this bogus
node because it doesn't seem to be used at all.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Wed, 13 Oct 2021 16:14:00 +0000 (18:14 +0200)]
armv8: ls1028a: use the official compatible string for the GPU
There is no "fsl,ls1028a-gpu" compatible string. It is solely for the
proprietary driver which will never be open source. Lately, linux gained
support for the open source etnaviv driver for the GPU (although there
is still support for the DisplayPort PHY missing to get actual graphics
output). Thus, instead of supporting some proprietary driver, switch
over to the open source one, which also have an official device tree
binding.
Cc: Andy Tang <andy.tang@nxp.com> Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Kuldeep Singh [Fri, 1 Oct 2021 10:54:24 +0000 (16:24 +0530)]
arm: dts: ls1088a: Update qspi node properties
Remove "num-cs" property from device-tree as it is no longer used by
qspi driver anymore.
Also, specify status as "disabled" and enable qspi support in respective
board dts files. This will also help in aligning node properties with
other board properties.
Michael Walle [Tue, 9 Nov 2021 09:18:51 +0000 (14:48 +0530)]
board: sl28: enable EFI UpdateCapsule support
Enable support for update over EFI UpdateCapsule mechanism. This board
doesn't support setting EFI variables after ExitBootservices().
Therefore, we are also enabling EFI_IGNORE_OSINDICATIONS.
Signed-off-by: Michael Walle <michael@walle.cc>
[Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Wed, 29 Sep 2021 11:39:10 +0000 (13:39 +0200)]
board: sl28: generate FIT update image
Generate a FIT update image during build. The image will be called
"u-boot.update" and can be used to build an EFI UpdateCapsule or during
DFU mode. Although, the latter isn't supported because there is no USB
OTG driver yet.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Increase fdt blob size for lx2160 and lx2162 series
to fix below errors/warnings during device tree fixup.
Unable to update property /soc/spi@2100000:status, err=FDT_ERR_NOSPACE
Unable to update property /soc/spi@2110000:status, err=FDT_ERR_NOSPACE
Unable to update property /soc/spi@2120000:status, err=FDT_ERR_NOSPACE
WARNING: could not set reg FDT_ERR_NOSPACE.
WARNING unable to set iommus: FDT_ERR_NOSPACE
Alban Bedel [Mon, 6 Sep 2021 14:32:56 +0000 (16:32 +0200)]
armv8: fsl-layerscape: Erratum A010315 needs PCIE support
Disabling PCIE support currently lead to a crash because the code for
erratum A010315 is still run. Add a conditional to only select
CONFIG_SYS_FSL_ERRATUM_A010315 when CONFIG_PCIE_LAYERSCAPE is enabled.
Signed-off-by: Alban Bedel <alban.bedel@aerq.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
UEFI
* Provide unit test for the EFI_TCG2_PROTOCOL
* Implement add EFI_TCG2_PROTOCOL.SubmitCommand
* Start the implementation of a 64 bit EFI app
* Reduce rcar3_salvator-x image size
Masahisa Kojima [Thu, 4 Nov 2021 10:45:46 +0000 (19:45 +0900)]
efi_selftest: add selftest for EFI_TCG2_PROTOCOL and Measured Boot
This commit adds the missing EFI_TCG2_PROTOCOL selftest
and Measured Boot selftest in lib/efi_selftest.
This selftest includes PE/COFF image measurement test, some PCR values are
different in each architecture. With that, this commit also adds pre-built
versions of lib/efi_selftest/efi_miniapp_file_image_exit.c for PE/COFF
image measurement test for 32-bit arm, arm64, ia32, x86_64, riscv32 and
riscv64. Prebuilding avoids the problem of reproducible builds.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Make the test 'onrequest'.
Add code comments to the includes with the binaries. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Simon Glass [Thu, 4 Nov 2021 03:09:10 +0000 (21:09 -0600)]
efi: Add video support to the app
The current EFI video driver only works when running in the stub. In that
case the stub calls boot services (before jumping to U-Boot proper) and
copies the graphics info over to the efi table. This is necessary because
the stub exits boot services before jumping to U-Boot.
The app maintains access to boot services throughout its life, so does not
need to do this. Update the driver to support calling boot services
directly.
Enable video output for the app. Note that this uses the
EFI_GRAPHICS_OUTPUT_PROTOCOL protocol, even though it mentions vesa.
Simon Glass [Thu, 4 Nov 2021 03:09:06 +0000 (21:09 -0600)]
x86: Create a 32/64-bit selection for the app
Most EFI implementations use 64-bit but U-Boot only supports running as
a 32-bit app at present. While efi-x86_payload64 does boot from 64-bit
UEFI it immediately changes back to 32-bit before starting U-Boot.
In order to support a 64-bit U-Boot app, update the Kconfig to add an
option for 32/64 bit. Update the prompt for the existing option so it is
clear it relates to the stub. Move both up to just under the choice that
controls them, since this looks better and the menu.
Use CONFIG_EFI_APP in the Makefile instead of CONFIG_TARGET_EFI_APP,
since the latter is specific to a single target and we will have two.
Memory size is set to 32MB for now so that it can run on qemu without
increasing the default memory size. We may need to increase the default
later.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Simon Glass [Thu, 4 Nov 2021 03:09:05 +0000 (21:09 -0600)]
efi: Drop the OF_EMBED warning for EFI
For the EFI app, we must embed the devicetree in the ELF file since that
is the only thing that is run by UEFI. Drop the warning to avoid
confusion.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Simon Glass [Thu, 4 Nov 2021 03:09:03 +0000 (21:09 -0600)]
efi: Add a script to build an image for testing on UEFI
It is quite complicated to run U-Boot on QEMU since we have four
different builds and they must use different versions of qemu and the
UEFI binaries.
Add a script to help. It requires U-Boot itself to be built. Once that
is done you can use this script to build an image for use with qemu and
optionally run it.
Masahisa Kojima [Thu, 4 Nov 2021 13:59:16 +0000 (22:59 +0900)]
efi_loader: add EFI_TCG2_PROTOCOL.SubmitCommand
This commit adds the EFI_TCG2_PROTOCOL.SubmitCommand
required in the TCG PC Client PFP spec.
SubmitCommand enables to send the raw command to the TPM device.
To implement this api, tpm2_submit_command() is added
into tpm-v2.c.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Thomas Huth [Tue, 26 Oct 2021 06:13:04 +0000 (08:13 +0200)]
doc: Remove the obsolete README.AMCC-eval-boards-cleanup file
The related boards have been removed four years ago already, in
commit 98f705c9cefd ("powerpc: remove 4xx support"), so this README
file is not required anymore.
Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Stefan Roese <sr@denx.de>
Stefan Roese [Thu, 21 Oct 2021 05:20:12 +0000 (07:20 +0200)]
doc: Remove obsolete doc/README.nand-boot-ppc440
The PPC440 support has been removed in commit 98f705c9ce
("powerpc: remove 4xx support"). This patch removes this obsolete
file as well.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Cc: Thomas Huth <thuth@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com>
Tom Rini [Sun, 31 Oct 2021 03:03:48 +0000 (23:03 -0400)]
spl: Make use of CONFIG_IS_ENABLED(OS_BOOT) in SPL/TPL common code paths
When building a system that has both TPL and SPL_OS_BOOT, code which
tests for CONFIG_SPL_OS_BOOT will be built and enabled in TPL, which is
not correct. While there is no CONFIG_TPL_OS_BOOT symbol at this time
(and likely will not ever be) we can use CONFIG_IS_ENABLED(OS_BOOT) in
these common paths to ensure we only compile these parts in the SPL
case.
Tom Rini [Wed, 20 Oct 2021 01:10:14 +0000 (21:10 -0400)]
fs: yaffs2: Finish Kconfig migration
For the symbols which are both hard-coded as enabled and used, move to
Kconfig. The rest of the CONFIG_YAFFS namespace is unselected anywhere,
so we leave it as is.
Samuel Holland [Thu, 4 Nov 2021 03:55:16 +0000 (22:55 -0500)]
sunxi: Use sysreset framework for poweroff/reset
Instead of hardcoding the watchdog for reset, and the PMIC for poweroff,
use the sysreset framework to manage the available poweroff/reset
backends. This allows (as examples) using the PMIC to do a cold reset,
and using a GPIO to power off H3/H5 boards lacking a PMIC. Furthermore,
it removes the need to hardcode watchdog MMIO addresses, since the
sysreset backends can be discovered using the device tree.
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Stefan Roese <sr@denx.de>
Samuel Holland [Thu, 4 Nov 2021 03:55:15 +0000 (22:55 -0500)]
sunxi: Avoid duplicate reset_cpu with SYSRESET enabled
The sysreset uclass unconditionally provides a definition of the
reset_cpu() function. So does the sunxi board code. Fix the build with
SYSRESET enabled by omitting the function from the board code in that
case. The code still needs to be kept around for use in SPL.
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Stefan Roese <sr@denx.de>
Samuel Holland [Thu, 4 Nov 2021 03:55:14 +0000 (22:55 -0500)]
watchdog: Automatically register device with sysreset
Add an option to automatically register watchdog devices with the
wdt_reboot driver for use with sysreset. This allows sysreset to be a
drop-in replacement for platform-specific watchdog reset code, without
needing any device tree changes.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Stefan Roese <sr@denx.de>
Samuel Holland [Thu, 4 Nov 2021 03:55:13 +0000 (22:55 -0500)]
sysreset: watchdog: Move watchdog reference to plat data
Currently, the wdt_reboot driver always gets its watchdog device
reference from an OF node. This prevents selecting a watchdog at
runtime. Move the watchdog device reference to the plat data, so
the driver can be bound with the reference pre-provided. The
reference will still be acquired from the OF node if it is not
already provided.
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Stefan Roese <sr@denx.de>
Samuel Holland [Thu, 4 Nov 2021 03:55:12 +0000 (22:55 -0500)]
sysreset: Mark driver probe functions as static
These driver probe functions are not (and should not be) called from
outside the respective driver source files. Therefore, the functions
should be marked static.
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Stefan Roese <sr@denx.de>
Samuel Holland [Thu, 4 Nov 2021 03:55:11 +0000 (22:55 -0500)]
sysreset: Add uclass Kconfig dependency to drivers
None of the sysreset drivers do anything beyond providing sysreset
uclass ops. They should depend on the sysreset uclass.
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Stefan Roese <sr@denx.de>
- pci_mvebu: Fix access to config space and PCIe Root Port (Pali)
- a37xx: pci: Program the data strobe for config read requests (Pali)
- kwboot: Misc improvements and fixes (Pali)
Chunfeng Yun [Thu, 21 Oct 2021 05:33:07 +0000 (13:33 +0800)]
usb: mtu3: flush cache for the first GPD when allocate GPD ring
When allocate the GPD ring, and tell its address to the controller, then
the driver starts or resumes the QMU, the controller will try to access
the first GPD, so need flush the first one to avoid wrong GPD status.
Reported-by: Xin Lin <Xin.Lin@mediatek.com> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Pali Rohár [Mon, 1 Nov 2021 09:12:51 +0000 (10:12 +0100)]
arm: a37xx: pci: Program the data strobe for config read requests
According to the Armada 3720 Functional Specification Data Strobe applies
for both read and write config requests.
Data strobe bits configure which bytes from the start address should be
returned for read request. Set value 0xf (all 4 bits) into Data Strobe
register to read all four bytes from specified 32-bit config space
register. Same value for Data Strobe register is programmed by Linux
pci-aardvark.c driver for config read requests.
Without this patch pci-aardvark driver sets data strobe register only
during config write operations. So any followup config read operations
could result with just partial datai returned (if previous write operation
was not 32-bit wide). This patch fixes it and ensures that config read
operations always read all bytes from requested register.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Mon, 1 Nov 2021 13:00:02 +0000 (14:00 +0100)]
tools: kwboot: Do not send magic seq when changing baudrate back to 115200
After successful transfer of whole image only two things can happen:
- BootROM starts execution of data block, which changes UART baudrate
back to 115200 Bd,
- board crashes and causes CPU reset
In both cases UART baudrate is reset to the default speed. So there is
no need to send special magic sequence to inform kwboot that baudrate is
going to be reset and kwboot does not need to wait for this event and
can do it immediately after BootROM acknowledges end of xmodem transfer.
Move ARM code for sending magic sequence from main baudrate change
section to binhdr_pre section which is executed only before changing
baudrate from the default value of 115200 Bd to some new value. Remove
kwboot code waiting for magic sequence after successful xmodem transfer.
Rationale: sometimes when using very high UART speeds, magic sequence is
damaged and kwboot fails at this last stage. Removal of this magic
sequence makes booting more stable.
Data transfer protocol (xmodem) is using checksums and retransmit, so it
already deals with possible errors on transfer line.
Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Wed, 27 Oct 2021 18:57:02 +0000 (20:57 +0200)]
tools: kwboot: Do not use stack when setting baudrate back to default value
The ARM code we inject into the image to change baudrate back to the
default value of 115200 Baud, which is run after successful UART transfer
of the whole image, cannot use stack as at this stage stack pointer is not
initialized yet.
Stack can only be used when BootROM is executing binary header, to
preserve state of registers, since BootROM expects that.
Change the ARM baudrate code to not use stack at all and put binary
header specific pre + post code (which stores and restores registers) into
separate arrays.
The baudrate change code now jumps at it's end and expects that there is
either code which returns to the BootROM or jumps to the original exec
address.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Wed, 27 Oct 2021 18:57:01 +0000 (20:57 +0200)]
tools: kwboot: Replace ARM mov + movt instruction pair by mov + orr
Older Armada SoCs have custom ARMv5te compatible core which does not
support movt instruction. So replace mov + movt instruction pair used for
immediate move construction by mov + orr instructions which are supported
also by ARMv5te.
After this change kwboot ARM code should be compatible with any 32-bit ARM
core compatible by ARMv2 or new. At least GNU AS does not throw any error
or warning.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Wed, 27 Oct 2021 18:57:00 +0000 (20:57 +0200)]
tools: kwboot: Increase delay after changing baudrate in ARM code
Increase loop cycles from 600000 to 2998272, which should increase delay
from 1ms to about 5ms on 1200 MHz CPU.
The Number 2998272 was chosen as the nearest value around 3000000 which can
be encoded into one ARM mov instruction. It avoids usage of movt instruction
which is not supported by ARMv5te cores.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Wed, 27 Oct 2021 18:56:59 +0000 (20:56 +0200)]
tools: kwboot: Do not call tcdrain() after each sent packet
Kwboot puts each xmodem packet to kernel queue, then waits until all bytes
of that packet are transmitted over UART and then waits for xmodem reply
until it is received into kernel queue.
If some reply is received during the time we are waiting until all bytes
are transmitted, then kernel puts them into the queue and returns it to
kwboot in next read() call.
So there is no need to wait (with tcdrain() function) until all bytes from
xmodem packet are transmitted over UART, since any reply received either
during that time or after is returned to kwboot with the next read().
Therefore do not call tcdrain() after each xmodem packet sent. Instead
directly wait for any reply after putting xmodem packet into write kernel
queue.
This change could speed up xmodem transfer in case tcdrain() function waits
for a longer time.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Wed, 27 Oct 2021 18:56:58 +0000 (20:56 +0200)]
tools: kwboot: Fix sending retry of last header packet
After the trasfer of last header packet, it is possible that baudrate
change pattern is received, and also that NAK byte is received so that
the packet should be sent again.
Thus we should not clear the baudrate change state when sending retry
of that packet.
Move code for initializing state variables from kwboot_xm_recv_reply()
to kwboot_xm_sendblock().
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Mon, 25 Oct 2021 13:13:04 +0000 (15:13 +0200)]
tools: kwboot: Resend first 3 xmodem retry packets immediately
Currently when kwboot receive some garbage reply which does not understand,
it waits 1s before it tries to resend packet again.
The most common error on UART is that receiver sees some bit flipped which
results in invalid reply.
This behavior slows down xmodem transfer over UART as basically on every
error kwboot is waiting one second.
To fix this, try to resend xmodem packet for first 3 attempts immediately
without any delay. If broken reply is received also after the 3 attempts,
continue retrying with 1s delay like it was before.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Mon, 25 Oct 2021 13:13:02 +0000 (15:13 +0200)]
tools: kwboot: Calculate real used space in kwbimage header when calling kwboot_img_grow_hdr()
Size of the header stored in kwbimage may be larger than real used size in
the kwbimage header. If there is unused space in kwbimage header then use
it for growing it. So update code to calculate used space of kwbimage
header.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Mon, 25 Oct 2021 13:13:00 +0000 (15:13 +0200)]
tools: kwboot: Simplify code for aligning image header
Expression (hdrsz % KWBOOT_XM_BLKSZ) is non-zero therefore expression
(KWBOOT_XM_BLKSZ - hdrsz % KWBOOT_XM_BLKSZ) is always less than value
KWBOOT_XM_BLKSZ. So there is no need to add another modulo. Also rename
variable `offset` to `grow` which better describes what is stored in
this variable.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Mon, 25 Oct 2021 13:12:59 +0000 (15:12 +0200)]
tools: kwboot: Show verbose message when waiting for baudrate change magic
It is hard to debug why kwboot is failing when the last message is
'Finishing transfer' and no additional output. So show verbose message when
kwboot finished transfer and is waiting for baudrate change magic sequence.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Mon, 25 Oct 2021 13:12:58 +0000 (15:12 +0200)]
tools: kwboot: Correctly set configuration of UART for BootROM messages
For kwbimage v1, tell BootROM to send BootROM messages to UART port number
0 (used also for UART booting) with default baudrate (which should be
115200) and do not touch UART MPP configuration.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Mon, 25 Oct 2021 13:12:57 +0000 (15:12 +0200)]
tools: kwboot: Recalculate 4-byte data checksum after injecting baudrate code
If data part of image is modified, update 4-byte data checksum.
It looks like A385 BootROM does not verify this checksum for image
loaded via UART, but we do not know if other BootROMs are also ignoring
it. It is always better to provide correct checksum.
Signed-off-by: Pali Rohár <pali@kernel.org>
[ refactored ] Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Mon, 25 Oct 2021 13:12:56 +0000 (15:12 +0200)]
tools: kwboot: Inject baudrate change back code after data part
Some vendor U-Boot kwbimage binaries (e.g. those for A375) have load
address set to zero. Therefore it is not possible to inject code which
changes baudrate back to 115200 Bd before the data part.
So instead inject it after the data part and change kwbimage execution
address to that offset. Also store original execution address into
baudrate change code, so after it changes baudrate back to 115200 Bd, it
can jump to orignal address.
Signed-off-by: Pali Rohár <pali@kernel.org>
[ refactored ] Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Mon, 25 Oct 2021 13:12:54 +0000 (15:12 +0200)]
tools: kwboot: Reserve enough space for patching kwbimage in memory
SPI image header and data parts do not have to be aligned to 128 byte
xmodem block size. So reserve additional memory for aligning header part
and additional memory for aligning data part.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Mon, 25 Oct 2021 13:12:53 +0000 (15:12 +0200)]
tools: kwboot: Fix initialization of tty device
Explicitly disable 2 stop bits by clearing CSTOPB flag, disable modem
control flow by clearing CRTSCTS flag and do not send hangup after closing
device by clearing HUPCL flag.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Fri, 22 Oct 2021 14:22:13 +0000 (16:22 +0200)]
pci: pci_mvebu: Do not automatically enable bus mastering on PCI Bridge
Now that PCI Bridge is working, U-Boot's CONFIG_PCI_PNP code automatically
enables memory access and bus mastering when it is needed. So do not
prematurely enable memory access and bus mastering.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Fri, 22 Oct 2021 14:22:12 +0000 (16:22 +0200)]
pci: pci_mvebu: Fix place of link up detection
PCI Bridge is always accessible also when link is down. So move detection
of link up from mvebu_pcie_of_to_plat() function to mvebu_pcie_valid_addr()
function which is used when accessing PCI config space.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Fri, 22 Oct 2021 14:22:10 +0000 (16:22 +0200)]
pci: pci_mvebu: Properly configure and use PCI Bridge (PCIe Root Port)
The mysterious "Memory controller" PCI device which is present in PCI
config space is improperly configured and crippled PCI Bridge which acts
as PCIe Root Port for endpoint PCIe card.
This PCI Bridge reports in PCI config space incorrect Class Code (Memory
Controller) and incorrect Header Type (Type 0). It looks like HW bug in
mvebu PCIe controller but apparently it can be changed via mvebu registers
to correct values.
The worst thing is that this PCI Bridge is crippled and its PCI config
registers in range 0x10-0x34 alias access to internal mvebu registers which
have different functionality as PCI Bridge registers. Moreover,
configuration of PCI primary and secondary bus numbers (registers 0x18
and 0x19) is done via totally different mvebu registers via totally strange
method and cannot be done via PCI Bridge config space.
Due to above fact about PCI config range 0x10-0x34, allocate a private
cfgcache[] buffer in the driver, to which PCI config access requests to
the 0x10-0x34 space will be redirected in mvebu_pcie_read_config() and
mvebu_pcie_write_config() functions. Function mvebu_pcie_write_config()
will also catch writes to PCI_PRIMARY_BUS (0x18) and PCI_SECONDARY_BUS
(0x19) registers and set PCI Bridge primary and secondary bus numbers via
mvebu's own method.
Also, Expansion ROM Base Address register (0x38) is available, but at
different offset 0x30. So recalculate register offset before accessing PCI
config space.
After these steps U-Boot sees working PCI Bridge and CONFIG_PCI_PNP code
can finally start enumerating all PCIe devices correctly, even with more
complicated PCI topology. So update also mvebu_pcie_valid_addr() function
to reflect state of the real device topology.
Each PCIe port is de-facto isolated and every PCI Bridge which is part of
PCIe Root Complex is also isolated, so put them on separate PCI buses as
(local) device 0.
U-Boot already supports enumerating separate PCI buses, real (HW) bus
number can be retrieved by "PCI_BUS(bdf) - dev_seq(bus)" code, so update
config read/write functions to properly handle more complicated tree
topologies (e.g. when a PCIe switch with multiple PCI buses is connected
to the PCIe port).
Local bus number and local device number on mvebu are used for determining
which config request type is used (Type 0 vs Type 1). On normal non-broken
PCIe hardware it is done by primary and secondary bus numbers. So correctly
translate settings between these numbers to ensure that correct config
requests are sent over the PCIe bus.
As bus numbers are correctly re-configured, it does not make sense to print
some initial bogus configuration during probe, so remove this debug code.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Fri, 22 Oct 2021 14:22:09 +0000 (16:22 +0200)]
pci: pci_mvebu: Fix read_config() with PCI_SIZE_8 or PCI_SIZE_16
When reading 8 or 16 bits from config space, use appropriate readb() or
readw() calls. This ensures that PCIe controller does not read more bits
from endpoint card as asked by read_config() function.
Technically there should not be an issue with reading data from config
space which are not later used as there are no clear-by-read registers.
But it is better to use correct read operation based on requested size.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
projects / u-boot.git / log
