Tom Rini [Mon, 20 Jun 2022 12:09:24 +0000 (08:09 -0400)]
Merge tag 'u-boot-stm32-20220620' of https://source.denx.de/u-boot/custodians/u-boot-stm into next
- Add STM32MP13 SoCs support with associated board STM32M135F-DK
- Correct livetree support in stm32mp1 boards
- Activate livetree for stm32mp15 DHSOM boards
Michael Walle [Mon, 30 May 2022 21:02:09 +0000 (23:02 +0200)]
board: sl28: support 8 GiB memory
The board supports up to 8 GiB memory. The memory is soldered on the
board but the configuration is equivalent to a dual chip select, dual
rank DIMM module.
Michael Walle [Mon, 30 May 2022 21:02:07 +0000 (23:02 +0200)]
board: sl28: set CPO value
With a 8GiB memory board, it seems that the "very unlikely event" of a
DDR initialization with non-optimal values are not really that unlikely.
It happens in about every other reboot. As described in erratum
A-009942, preset the DEBUG_28 register with an optimal value. The value
iself depends on the memory configuration of the board, but the used
value seems to work well for all variants.
Michael Walle [Mon, 30 May 2022 21:02:05 +0000 (23:02 +0200)]
armv8: layerscape: add missing RCW source defines
A board might need to get the source of the RCW word, which is also the
boot source in most cases.
These defines are taken from the LS1028A and I expect they are the same
across the SoCs with the same chassis, after all, there was already a
reset source for NOR flash.
Pali Rohár [Thu, 26 May 2022 08:52:27 +0000 (10:52 +0200)]
board: freescale: p1_p2_rdb_pc: Move boot reset macros to p1_p2_bootsrc.h
Code for changing boot source is platform generic and can be used by any
P1* and P2* compatible RDB board. Not only by boards which use config
header file p1_p2_rdb_pc.h.
So move this code from p1_p2_rdb_pc.h to p1_p2_bootsrc.h and cleanup macros
for generating boot source env variables in CONFIG_EXTRA_ENV_SETTINGS.
This allows to use code for resetting board and rebooting to other boot
source also by other boards in future.
Pali Rohár [Wed, 11 May 2022 18:27:13 +0000 (20:27 +0200)]
mmc: fsl_esdhc: Add new config option for default fallback mode
Currently default fallback SDHC mode is 1-bit. Add new config option
CONFIG_SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH to allow specifying default fallback
mode. This is useful e.g. for SPL builds which loads other parts from SD
card during boot process.
Pali Rohár [Wed, 11 May 2022 18:27:12 +0000 (20:27 +0200)]
mmc: fsl_esdhc: Set fallback mode to 1-bit
8-bit mode is not supported by SD cards and on P2020 are four SDHC pins
shared with SPI (so if P2020 board have also SPI then only 4-bit SDHC mode
is provided). So 8-bit SDHC mode is really bad default.
When max bus width is not provided then set mode to 1-bit. This mode is
supported by all cards, so it is the best option for fallback mode.
Also P2020 bootrom sets mode to 1-bit when booting from SD/MMC card.
Alison Wang [Tue, 10 May 2022 10:29:10 +0000 (18:29 +0800)]
ls1028a: hdp: Add config support for HDP firmware loading
This patch adds config support for HDP firmware loading on LS1028A.
Signed-off-by: Oliver Brown <oliver.brown@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Pali Rohár [Sun, 1 May 2022 15:45:58 +0000 (17:45 +0200)]
powerpc: fsl_law: Add definition for first PCIe target interface
Header file asm/fsl_law.h already provides correct definition for second
and third PCIe controller (LAW_TRGT_IF_PCIE_2 and LAW_TRGT_IF_PCIE_3). But
is missing definition for the first PCIe controller (LAW_TRGT_IF_PCIE_1).
Note that existing definition for LAW_TRGT_IF_PCIE_2 and LAW_TRGT_IF_PCIE_3
are slightly complicated, but are really correct for P2020 platform.
When CONFIG_WDT is enabled then non-DM watchdog code cannot be used due to
conflicting functions like watchdog_reset(). So disable compilation of
mpc85xx watchdog_reset() function when CONFIG_WDT is enabled.
Sean Anderson [Fri, 22 Apr 2022 18:34:19 +0000 (14:34 -0400)]
ARM: dts: ls1021a: update the clockgen node
QorIQ platforms now use different clock bindings. Although we don't use
the device tree for clocks on this platform, it is helpful to sync it
because then the bindings will more closely match Linux. Additionally,
it allows for using more clock fractions (such as platform/4).
This corresponds to Linux commit b6f5e7019391 ("ARM: dts: ls1021a:
update the clockgen node").
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Sean Anderson [Fri, 22 Apr 2022 18:34:18 +0000 (14:34 -0400)]
arm: layerscape: Add sfp driver
This adds a driver for the Security Fuse Processor (SFP) present on
LS1012A, LS1021A, LS1043A, and LS1046A processors. It holds the
Super-Root Key (SRK), One-Time-Programmable Master Key (OTPMK), and
other "security" related fuses. Similar devices (sharing the same name)
are present on other processors, but for the moment this just supports
the LS2 variants.
The mirror registers are loaded during power-on reset. All mirror
registers must be programmed or read at once. Because of this, `fuse
prog` will program all fuses, even though only one might be specified.
To prevent accidentally burning through all your fuse programming cycles
with something like `fuse prog 0 0 A B C D`, we limit ourselves to one
programming cycle per reset. Fuses are numbered based on their address.
The fuse at 0x1e80200 is 0, the fuse at 0x1e80204 is 1, etc.
The TA_PROG_SFP supply must be enabled when programming fuses, but must
be disabled when reading them. Typically this supply is enabled by
inserting a jumper or by setting a register in the board's FPGA. I've
also added support for using a regulator. This could be helpful for
automatically issuing the FPGA write, or for toggling a GPIO controlling
the supply.
I suggest using the following procedure for programming:
1. Override the fuses you wish to program
=> fuse override 0 2 A B C D
2. Inspect the values and ensure that they are what you expect
=> fuse sense 0 2 4
3. Enable TA_PROG_SFP
4. Issue a program command using OSPR0 as a dummy. Since it contains the
write-protect bit you will usually want to write it last anyway.
=> fuse prog 0 0 0
5. Disable TA_PROG_SFP
6. Read back the fuses and ensure they are correct
=> fuse read 0 2 4
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Patrick Delaunay [Wed, 15 Jun 2022 17:41:48 +0000 (19:41 +0200)]
configs: stm32mp: cleanup the stm32mp15 file
Remove STM32_SYSRAM_END and clean the comments in stm32mp15_common.h file
after moving some CONFIG to Kconfig: CONFIG_SYS_CBSIZE,
CONFIG_SPL_MAX_FOOTPRINT, CONFIG_SYS_SPL_MALLOC_START and
CONFIG_SYS_SPL_MALLOC_SIZE.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
stm32mp: stpmic1: remove the debug unit request by debugger
Depending on backup register value, U-Boot SPL maintains the debug unit
powered-on for debugging purpose; only BUCK1 is required for powering
the debug unit, so revert the setting for all the other power lanes,
except BUCK3 that has to be always on.
To be functional this patch requires a modification in the debugger
,openocd for example, to update the STM32MP15 backup register when it is
required to debug SPL after reset. After deeper analysis this behavior
will be never supported in tools so the associated code, will be never
used and the associated code can be removed.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Thu, 19 May 2022 15:56:46 +0000 (17:56 +0200)]
misc: stm32mp13: introduce STM32MP13 RCC driver
Add the MISC RCC driver for STM32MP13, and bind it to the RCC reset
driver, required for initial support.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Sean Anderson <seanga2@gmail.com>
Change-Id: Ida11c15462caf140f87b1e3239efa2b8a689acb9
Patrick Delaunay [Thu, 19 May 2022 15:56:45 +0000 (17:56 +0200)]
clk: Add directory for STM32 clock drivers
Add a directory in drivers/clk to regroup the clock drivers for all
STM32 Soc with CONFIG_ARCH_STM32 (MCUs with cortex M) or
CONFIG_ARCH_STM32MP (MPUs with cortex A).
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Grzegorz Szymaszek <gszymaszek@short.pl> Acked-by: Sean Anderson <seanga2@gmail.com>
Change-Id: I955af307963f732167396f0157a30cf2fc91f150
Patrick Delaunay [Fri, 20 May 2022 16:24:51 +0000 (18:24 +0200)]
mmc: stm32_sdmmc2: make reset property optional
Although not recommended, the reset property could be made optional.
This way the driver will probe even if no reset property is provided
in an sdmmc node in DT. This reset is already optional in Linux.
Patrick Delaunay [Fri, 20 May 2022 16:24:50 +0000 (18:24 +0200)]
ram: stm32mp1: add support of STM32MP13x
Add support for new compatible "st,stm32mp13-ddr" to manage the
DDR sub system (Controller and PHY) in STM32MP13x SOC:
- only one AXI port
- support of 16 port output (MEMC_DRAM_DATA_WIDTH = 2)
The STM32MP15x SOC have 2 AXI ports and 32 bits support.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Peng Fan [Sat, 11 Jun 2022 12:21:01 +0000 (20:21 +0800)]
configs: drop CONFIG_SPL_ABORT_ON_RAW_IMAGE
CONFIG_SPL_RAW_IMAGE_SUPPORT default y has been used to replace
CONFIG_SPL_ABORT_ON_RAW_IMAGE for quite some time, so drop
CONFIG_SPL_ABORT_ON_RAW_IMAGE.
Peng Fan [Sat, 11 Jun 2022 12:21:00 +0000 (20:21 +0800)]
imx: kontron-sl-mx8mm: enable DM_SERIAL
Enable CONFIG_DM_SERIAL. uart and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_init to make sure driver
model work.
Peng Fan [Sat, 11 Jun 2022 12:20:59 +0000 (20:20 +0800)]
imx: imx8mn_var_som: enable DM_SERIAL
Enable CONFIG_DM_SERIAL. uart and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_init to make sure driver
model work.
Peng Fan [Sat, 11 Jun 2022 12:20:58 +0000 (20:20 +0800)]
imx: imx8m[m/p]_phycore: Enable DM_SERIAL
Enable CONFIG_DM_SERIAL. uart and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_early_init to make sure driver
model work.
Peng Fan [Sat, 11 Jun 2022 12:20:57 +0000 (20:20 +0800)]
imx: imx8mm_icore: Enable SPL_DM_SERIAL
Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_early_init to make sure driver
model work.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
Peng Fan [Sat, 11 Jun 2022 12:20:56 +0000 (20:20 +0800)]
imx: imx8mm-cl-iot-gate: Enable DM_SERIAL
Enable CONFIG_DM_SERIAL. uart3 and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_early_init to make sure driver
model work.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
Peng Fan [Sat, 11 Jun 2022 12:20:55 +0000 (20:20 +0800)]
imx: imx8m[m/n]_beacon: Enable SPL_DM_SERIAL
Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_init to make sure driver
model work.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Tested-by: Adam Ford <aford173@gmail.com> #imx8mm_beacon Reviewed-by: Fabio Estevam <festevam@denx.de> Tested-by: Adam Ford <aford173@gmail.com> #imx8mn_beacon
Add am62x_evm_r5_defconfig for R5 SPL and am62x_evm_a53_defconfig for
A53 SPL and U-Boot support.
To keep the changes to minimum. Only UART And SD boot related configs
are included. This should serve as good starting point for new board
bringup with AM62x.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
[trini: Migrate a number of CONFIG symbols, have re-tested] Tested-by: Georgi Vlaev <g-vlaev@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
Nishanth Menon [Wed, 25 May 2022 08:08:48 +0000 (13:38 +0530)]
arm: dts: Add support for AM62-SK
AM62 StarterKit (SK) board is a low cost, small form factor board
designed for TI’s AM625 SoC. It supports the following interfaces:
* 2 GB DDR4 RAM
* x2 Gigabit Ethernet interfaces capable of working in Switch and MAC mode
* x1 HDMI Port with audio + x1 OLDI/LVDS Display interface for Dual Display
* x1 Headphone Jack
* x1 USB2.0 Hub with two Type A host and x1 USB Type-C DRP Port
* x1 UHS-1 capable µSD card slot
* 2.4/5 GHz WLAN + Bluetooth 4.2 through WL1837
* 512 Mbit OSPI flash
* x4 UART through UART-USB bridge
* XDS110 for onboard JTAG debug using USB
* Temperature sensors, user push buttons and LEDs
* 40-pin User Expansion Connector
* 24-pin header for peripherals in MCU island (I2C, UART, SPI, IO)
* 20-pin header for Programmable Realtime Unit (PRU) IO pins
* 15-pin CSI header
Add basic support for AM62-SK.
To keep the changes to minimum. Only UART And SD are supported at the
moment. This should serve as good example for adding new board support
based on AM62x SoC
Suman Anna [Wed, 25 May 2022 08:08:47 +0000 (13:38 +0530)]
board: ti: Introduce the basic files to support AM62 SK board
Add basic support for AM62 SK. This has 2GB DDR.
Note that stack for R5 SPL is in OCRAM @ 0x7000ffff so that is away from
BSS and does not step on BSS section
Add only the bare minimum required to support UART and SD.
Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Suman Anna [Wed, 25 May 2022 08:08:42 +0000 (13:38 +0530)]
arm: mach-k3: Introduce the basic files to support AM62
The AM62 SoC family is the follow on AM335x built on K3 Multicore SoC
architecture platform, providing ultra-low-power modes, dual display,
multi-sensor edge compute, security and other BOM-saving integration.
The AM62 SoC targets broad market to enable applications such as
Industrial HMI, PLC/CNC/Robot control, Medical Equipment, Building
Automation, Appliances and more.
Some highlights of this SoC are:
* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
Pin-to-pin compatible options for single and quad core are available.
* Cortex-M4F for general-purpose or safety usage.
* Dual display support, providing 24-bit RBG parallel interface and
OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display
resolution.
* Selectable GPUsupport, up to 8GFLOPS, providing better user experience
in 3D graphic display case and Android.
* PRU(Programmable Realtime Unit) support for customized programmable
interfaces/IOs.
* Integrated Giga-bit Ethernet switch supporting up to a total of two
external ports (TSN capable).
* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for
NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio,
1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
* Dedicated Centralized System Controller for Security, Power, and
Resource Management.
* Multiple low power modes support, ex: Deep sleep,Standby, MCU-only,
enabling battery powered system design.
AM625 is the first device of the family. Add DT bindings for the same.
More details can be found in the Technical Reference Manual:
https://www.ti.com/lit/pdf/spruiv7
Suman Anna [Wed, 25 May 2022 08:08:40 +0000 (13:38 +0530)]
dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM62
Add pinctrl macros for AM62x SoCs. These macro definitions are similar
to that of previous platforms, but adding new definitions to avoid any
naming confusions in the SoC dts files.
checkpatch insists the following error exists:
ERROR: Macros with complex values should be enclosed in parentheses
However, we do not need parentheses enclosing the values for this
macro as we do intend it to generate two separate values as has been
done for other similar platforms.
Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
drivers: mmc: am654_sdhci: Add new compatible for AM62 SoC
The phy used in the 8 bit instance has been changed to the phy used in 4
bit instance on AM62 SoC. This implies the phy configuration required for
both the instances of mmc are similar. Therefore, add a new compatible
for AM62 SoC using the driver data of am64 4 bit instance.
arm: mach-k3: am6_init: Fix the path and value's length in the fixup performed for usb boot
The node name of the bus in the device tree has changed. Also, the length
argument to be passed should be the length of new value. Therefore, fix the
path to usb device tree node as well as the length argument passed.
Masahisa Kojima [Tue, 17 May 2022 08:41:37 +0000 (17:41 +0900)]
spi: synquacer: wait until slave is deselected
synquacer_cs_set() function does not wait the chip select
is deasserted when the driver sets the DMSTOP to deselect
the slave.
This commit checks the Slave Select Released(SRS) bit to wait
until the slave is deselected.
Derald D. Woods [Mon, 16 May 2022 03:25:05 +0000 (22:25 -0500)]
ARM: omap3: evm: Fix 'fitImage' booting
This commit sets two additional variables in the default BOOTCOMMAND.
Adding 'boot=mmc' and 'addr_fit=0x8b000000' removes the need for a
special 'uEnv.txt' to be created. The 'addr_fit' variable is the key
piece here. It is normally defined as 0x90000000, in the macro
DEFAULT_FIT_TI_ARGS. For this OMAP34XX board, 0x8b000000 works without
touching other varibles. This was tested with a 'fitImage' created
using the following FIT source:
projects / u-boot.git / log
![2 years agoimx: imx8m[m/p]_phycore: Enable DM_SERIAL](/img/static/git-logo.png?p=u-boot.git;a=commit;h=64d118b27f96aed81c2922e20d2b5db9e32a465f){kind=link}
![2 years agoimx: imx8m[m/n]_beacon: Enable SPL_DM_SERIAL](/img/static/git-logo.png?p=u-boot.git;a=commit;h=d35130fef8a1c6a43a76fdcc5100d5d794084e93){kind=link}
