From: Michael Walle <[michael@walle.cc]>
Date: Mon, 31 Oct 2011 14:52:58 +0000 (+0530)
Subject: kirkwood: define CONFIG_SYS_CACHELINE_SIZE
X-Git-Tag: v2025.01-rc5-pxa1908~18516^2~67
X-Git-Url: http://git.dujemihanovic.xyz/img/static/git-logo.png?a=commitdiff_plain;h=f779d739d67653c0d77f50cb18c315b2d39de075;p=u-boot.git

kirkwood: define CONFIG_SYS_CACHELINE_SIZE

By default, on Kirkwood SoC DCache Lnd ICache line
lengths are 32 bytes long

Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
---

diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h
index f17f82d3f4..d1c199825f 100644
--- a/arch/arm/include/asm/arch-kirkwood/config.h
+++ b/arch/arm/include/asm/arch-kirkwood/config.h
@@ -41,7 +41,8 @@
 
 #include <asm/arch/kirkwood.h>
 #define CONFIG_ARM926EJS	1	/* Basic Architecture */
-
+#define CONFIG_SYS_CACHELINE_SIZE	32
+				/* default Dcache Line length for kirkwood */
 #define CONFIG_MD5	/* get_random_hex on krikwood needs MD5 support */
 #define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
 #define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */