From: Stefan Roese Date: Tue, 9 Oct 2018 06:59:04 +0000 (+0200) Subject: mips: mt76xx: lowlevel_init.S: Add missing memory controller reset in DDR init X-Git-Url: http://git.dujemihanovic.xyz/img/static/git-logo.png?a=commitdiff_plain;h=a8b0bf631308fd74a0216b1dc7eb74119303a0b3;p=u-boot.git mips: mt76xx: lowlevel_init.S: Add missing memory controller reset in DDR init This fixes an issue which has been noticed on the Gardena board, with the watchdog enabled, where the watdchdog reset (after a system hang) did result in reporting of 2.9 GiB and a hang after this. With this patch applied the memory controller is correctly reset and initialized again even after a watchdog reset. Signed-off-by: Stefan Roese Cc: Daniel Schwierzeck --- diff --git a/arch/mips/mach-mt7620/lowlevel_init.S b/arch/mips/mach-mt7620/lowlevel_init.S index 1a50f160fe..aa707e0de6 100644 --- a/arch/mips/mach-mt7620/lowlevel_init.S +++ b/arch/mips/mach-mt7620/lowlevel_init.S @@ -108,6 +108,12 @@ CPLL_READY: sw t3, 0(t0) CPLL_DONE: + /* Reset MC */ + lw t2, 0x34(s0) + ori t2, BIT(10) + sw t2, 0x34(s0) + nop + /* * SDR and DDR initialization: delay 200us */