From: Ovidiu Panait Date: Tue, 31 May 2022 18:14:27 +0000 (+0300) Subject: microblaze: cache: improve icache Kconfig options X-Git-Url: http://git.dujemihanovic.xyz/img/static/git-logo.png?a=commitdiff_plain;h=8daf89678e9a8ce4203d2df6c65d9ff17aad785a;p=u-boot.git microblaze: cache: improve icache Kconfig options Replace CONFIG_ICACHE with a Kconfig option more limited in scope - XILINX_MICROBLAZE0_USE_WIC. It should be enabled if the processor supports the "wic" (Write to Instruction Cache) instruction. It will be used to guard "wic" invocations in microblaze cache code. Signed-off-by: Ovidiu Panait Link: https://lore.kernel.org/r/20220531181435.3473549-6-ovpanait@gmail.com Signed-off-by: Michal Simek --- diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 11ccbcc9f2..ce157a79cc 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -39,10 +39,6 @@ config TARGET_MICROBLAZE_GENERIC endchoice -config ICACHE - bool "Enable icache support" - default y - source "board/xilinx/Kconfig" source "board/xilinx/microblaze-generic/Kconfig" diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c index 4e8e228a22..b6bbc215b3 100644 --- a/arch/microblaze/cpu/cache.c +++ b/arch/microblaze/cpu/cache.c @@ -58,14 +58,14 @@ void flush_cache(ulong addr, ulong size) { int i; for (i = 0; i < size; i += 4) { - asm volatile ( -#ifdef CONFIG_ICACHE + if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WIC)) { + asm volatile ( "wic %0, r0;" -#endif "nop;" : : "r" (addr + i) : "memory"); + } if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) { asm volatile ( diff --git a/board/xilinx/microblaze-generic/Kconfig b/board/xilinx/microblaze-generic/Kconfig index b00ce6f59a..98b4814b95 100644 --- a/board/xilinx/microblaze-generic/Kconfig +++ b/board/xilinx/microblaze-generic/Kconfig @@ -74,4 +74,15 @@ config SPL_XILINX_MICROBLAZE0_USE_WDC bool default XILINX_MICROBLAZE0_USE_WDC +config XILINX_MICROBLAZE0_USE_WIC + bool "MicroBlaze wic instruction support" + default y + help + Enable this option if the MicroBlaze processor is configured with + support for the "wic" (Write to Instruction Cache) instruction. + +config SPL_XILINX_MICROBLAZE0_USE_WIC + bool + default XILINX_MICROBLAZE0_USE_WIC + endif