From: Jernej Skrabec <jernej.skrabec@siol.net>
Date: Mon, 11 Jan 2021 20:11:38 +0000 (+0100)
Subject: sunxi: Add support for I2C on H6 like SoCs
X-Git-Url: http://git.dujemihanovic.xyz/img/static/git-logo.png?a=commitdiff_plain;h=57e7623776101ee7913997691e09436a393028d5;p=u-boot.git

sunxi: Add support for I2C on H6 like SoCs

I2C support, especially R_I2C port, will be needed in future. Upcoming
support for H616 will need R_I2C to adjust DRAM voltage.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
index 426069fc69..e83e84ab6c 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
@@ -297,6 +297,7 @@ struct sunxi_ccm_reg {
 
 /* Module gate/reset shift*/
 #define RESET_SHIFT			(16)
+#define GATE_SHIFT			(0)
 
 /* DRAM clock bit field */
 #define DRAM_MOD_RESET			BIT(30)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 36b142588f..edb9973cf2 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -730,7 +730,7 @@ config I2C3_ENABLE
 	See I2C0_ENABLE help text.
 endif
 
-if SUNXI_GEN_SUN6I
+if SUNXI_GEN_SUN6I || SUN50I_GEN_H6
 config R_I2C_ENABLE
 	bool "Enable the PRCM I2C/TWI controller"
 	# This is used for the pmic on H3
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index ba8a26eb0d..6bd466915c 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -2,6 +2,7 @@
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/prcm.h>
 
 #ifdef CONFIG_SPL_BUILD
 void clock_init_safe(void)
@@ -92,3 +93,31 @@ unsigned int clock_get_pll6(void)
 	/* The register defines PLL6-4X, not plain PLL6 */
 	return 24000000 / 4 * n / div1 / div2;
 }
+
+int clock_twi_onoff(int port, int state)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	struct sunxi_prcm_reg *const prcm =
+		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+	u32 value, *ptr;
+	int shift;
+
+	value = BIT(GATE_SHIFT) | BIT (RESET_SHIFT);
+
+	if (port == 5) {
+		shift = 0;
+		ptr = &prcm->twi_gate_reset;
+	} else {
+		shift = port;
+		ptr = &ccm->twi_gate_reset;
+	}
+
+	/* set the apb clock gate and reset for twi */
+	if (state)
+		setbits_le32(ptr, value << shift);
+	else
+		clrbits_le32(ptr, value << shift);
+
+	return 0;
+}