From: Tom Rini <trini@konsulko.com>
Date: Tue, 22 Nov 2022 17:33:48 +0000 (-0500)
Subject: Merge tag 'xilinx-for-v2023.01-rc3' of https://source.denx.de/u-boot/custodians/u... 
X-Git-Url: http://git.dujemihanovic.xyz/img/static/git-logo.png?a=commitdiff_plain;h=521277ec15eb794229403ec24b8c00a4ff02b0b6;p=u-boot.git

Merge tag 'xilinx-for-v2023.01-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2023.01-rc3

microblaze:
- Enable 32 bit addressing mode for SPIs

zynq:
- Minor DT fixes (PL clock enabling)

zynqmp:
- Disable watchdog by default
- Remove unused xlnx,eeprom chosen support
- Add missing symlink for vck190 SC revB
- Use mdio bus with ethernet-phy-id description

versal:
- Add mini qspi/ospi configuration

versal-net:
- Add soc driver
- Fix Kconfig entry for SOC
- Fix loading address location for MINI configuration
- Disable LMB for mini configuration

net:
- Fix ethernet-phy-id usage in the code

pinctrl:
- Revert high impedance/output enable support

timer:
- Fix timer relocation for Microblaze
- Fix timer wrap in 32bit Xilinx timer driver
---

521277ec15eb794229403ec24b8c00a4ff02b0b6