From: Quentin Schulz Date: Fri, 11 Nov 2022 11:25:48 +0000 (+0100) Subject: rockchip: px30: make watchdog and tsadc trigger a first global reset X-Git-Url: http://git.dujemihanovic.xyz/img/static/git-logo.png?a=commitdiff_plain;h=4b564460023a8cbf58d56f354e8ab45264770825;p=u-boot.git rockchip: px30: make watchdog and tsadc trigger a first global reset By default, the PX30 is configured for watchdog and tsadc to trigger a second global reset which is a more permissive reset than first global reset. From TRM part 1 "2.3 System Reset Solution": glb_srstn_1 will reset the all logic, and glb_srstn_2 will reset the all logic except GRF, SGRF and all GPIOs. This enforces that the watchdog and tsadc trigger glb_srstn_1 as similarly done for RK3399 in U-Boot (in SDRAM driver for some reason?), TF-A and Coreboot. Cc: Quentin Schulz Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index 0641e6af0f..ded03ffa51 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -234,6 +234,7 @@ enum { int arch_cpu_init(void) { static struct px30_grf * const grf = (void *)GRF_BASE; + static struct px30_cru * const cru = (void *)CRU_BASE; u32 __maybe_unused val; #ifdef CONFIG_SPL_BUILD @@ -285,6 +286,9 @@ int arch_cpu_init(void) /* Clear the force_jtag */ rk_clrreg(&grf->cpu_con[1], 1 << 7); + /* Make TSADC and WDT trigger a first global reset */ + clrsetbits_le32(&cru->glb_rst_con, 0x3, 0x3); + return 0; }