From: Emanuele Ghidoli Date: Wed, 15 May 2024 08:00:57 +0000 (+0200) Subject: arm: dts: k3-am625-verdin: Update autogenerated LPDDR4 configuration X-Git-Url: http://git.dujemihanovic.xyz/img/static/git-logo.png?a=commitdiff_plain;h=3bdc12856579666d74bf0f93a75c0b152ed56eea;p=u-boot.git arm: dts: k3-am625-verdin: Update autogenerated LPDDR4 configuration Update the autogenerated LPDDR4 configuration using the latest available SysConfig tool. This changes are cosmetic and are made to track the last used tool version. Signed-off-by: Emanuele Ghidoli --- diff --git a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi index 841541bb24..ca883ae82c 100644 --- a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi +++ b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * This file was generated with the - * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.10 - * Mon Dec 11 2023 17:07:35 GMT+0100 (Central European Standard Time) + * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.10.01 + * Tue May 14 2024 12:55:28 GMT+0200 (Central European Summer Time) * DDR Type: LPDDR4 * F0 = 50MHz F1 = NA F2 = 800MHz * Density (per channel): 16Gb @@ -10,9 +10,11 @@ * Number of Ranks: 1 */ + #define DDRSS_PLL_FHS_CNT 3 #define DDRSS_PLL_FREQUENCY_1 400000000 #define DDRSS_PLL_FREQUENCY_2 400000000 +#define DDRSS_SDRAM_IDX 15 #define DDRSS_CTL_0_DATA 0x00000B00