From: Gaurav Jain <gaurav.jain@nxp.com>
Date: Tue, 19 Apr 2022 05:22:28 +0000 (+0530)
Subject: crypto/fsl: add invalidate_dcache_range for hash output buffer
X-Git-Url: http://git.dujemihanovic.xyz/img/static/git-logo.png?a=commitdiff_plain;h=2c16bf2d14d7fbacafb5473f49487ba7f219e40c;p=u-boot.git

crypto/fsl: add invalidate_dcache_range for hash output buffer

HW accelerated hash operations are giving incorrect hash output.
so invalidate cache lines to avoid cache overwriting in DDR memory region.

caam_hash()
 -moved address alignment check in the beginning of function.
 -added invalidate_dcache_range for pout buffer before running descriptor.

Fixes: d7af2baa49 (crypto/fsl: Fix HW accelerated hash commands)
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
---

diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c
index 2379b70c2d..a52c4ac957 100644
--- a/drivers/crypto/fsl/fsl_hash.c
+++ b/drivers/crypto/fsl/fsl_hash.c
@@ -168,18 +168,18 @@ int caam_hash(const unsigned char *pbuf, unsigned int buf_len,
 	uint32_t *desc;
 	unsigned int size;
 
-	desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE);
-	if (!desc) {
-		debug("Not enough memory for descriptor allocation\n");
-		return -ENOMEM;
-	}
-
 	if (!IS_ALIGNED((uintptr_t)pbuf, ARCH_DMA_MINALIGN) ||
 	    !IS_ALIGNED((uintptr_t)pout, ARCH_DMA_MINALIGN)) {
 		puts("Error: Address arguments are not aligned\n");
 		return -EINVAL;
 	}
 
+	desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE);
+	if (!desc) {
+		debug("Not enough memory for descriptor allocation\n");
+		return -ENOMEM;
+	}
+
 	size = ALIGN(buf_len, ARCH_DMA_MINALIGN);
 	flush_dcache_range((unsigned long)pbuf, (unsigned long)pbuf + size);
 
@@ -190,6 +190,8 @@ int caam_hash(const unsigned char *pbuf, unsigned int buf_len,
 
 	size = ALIGN(sizeof(int) * MAX_CAAM_DESCSIZE, ARCH_DMA_MINALIGN);
 	flush_dcache_range((unsigned long)desc, (unsigned long)desc + size);
+	size = ALIGN(driver_hash[algo].digestsize, ARCH_DMA_MINALIGN);
+	invalidate_dcache_range((unsigned long)pout, (unsigned long)pout + size);
 
 	ret = run_descriptor_jr(desc);