From: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Date: Mon, 14 Nov 2022 10:33:46 +0000 (+0100)
Subject: rockchip: clk: add watchdog clock to px30_clk_enable
X-Git-Url: http://git.dujemihanovic.xyz/img/static/git-logo.png?a=commitdiff_plain;h=23b71addf90d2df7df591a84ed69300334b26ca9;p=u-boot.git

rockchip: clk: add watchdog clock to px30_clk_enable

Add the PCLK_WDT_NS clock to px30_clk_enable so that the watchdog driver
can probe since it wants to enable this clock.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---

diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c
index 5d467447a1..33a7348b9f 100644
--- a/drivers/clk/rockchip/clk_px30.c
+++ b/drivers/clk/rockchip/clk_px30.c
@@ -1415,6 +1415,9 @@ static int px30_clk_enable(struct clk *clk)
 	case SCLK_GMAC_RMII:
 		/* Required to successfully probe the Designware GMAC driver */
 		return 0;
+	case PCLK_WDT_NS:
+		/* Required to successfully probe the Designware watchdog driver */
+		return 0;
 	}
 
 	debug("%s: unsupported clk %ld\n", __func__, clk->id);