From: Peng Fan Date: Wed, 15 Jun 2016 02:53:02 +0000 (+0800) Subject: mmc: fsl: introduce wp_enable X-Git-Url: http://git.dujemihanovic.xyz/img/static/git-logo.png?a=commitdiff_plain;h=1483151e84161449c3f652a751a04e06b0723bff;p=u-boot.git mmc: fsl: introduce wp_enable Introudce wp_enable. To check WPSPL, wp_enable needs to be set to 1 in board code. Take i.MX6UL for example, for some boards, they do not use WP singal, so they does not configure USDHC1_WP_SELECT_INPUT, and its default value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and SION bit set. So USDHC controller can always get wp signal and WPSPL shows write protect and blocks driver continuing. This is not what we want to see, so add wp_enable, and if set to 0, just omit the WPSPL checking and this does not effect normal working of usdhc controller. If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0. Signed-off-by: Peng Fan Cc: Pantelis Antoniou Cc: York Sun Cc: Stefano Babic Cc: Fabio Estevam Tested-by: Fabio Estevam Reviewed-by: York Sun --- diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index c5f08ea08b..a865c7b47b 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -91,7 +91,9 @@ struct fsl_esdhc { * Following is used when Driver Model is enabled for MMC * @dev: pointer for the device * @non_removable: 0: removable; 1: non-removable + * @wp_enable: 1: enable checking wp; 0: no check * @cd_gpio: gpio for card detection + * @wp_gpio: gpio for write protection */ struct fsl_esdhc_priv { struct fsl_esdhc *esdhc_regs; @@ -101,7 +103,9 @@ struct fsl_esdhc_priv { struct mmc *mmc; struct udevice *dev; int non_removable; + int wp_enable; struct gpio_desc cd_gpio; + struct gpio_desc wp_gpio; }; /* Return the XFERTYP flags for a given command and data packet */ @@ -245,9 +249,12 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) #endif if (wml_value > WML_WR_WML_MAX) wml_value = WML_WR_WML_MAX_VAL; - if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { - printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); - return TIMEOUT; + if (priv->wp_enable) { + if ((esdhc_read32(®s->prsstat) & + PRSSTAT_WPSPL) == 0) { + printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); + return TIMEOUT; + } } esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, @@ -721,6 +728,7 @@ static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg, priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); priv->bus_width = cfg->max_bus_width; priv->sdhc_clk = cfg->sdhc_clk; + priv->wp_enable = cfg->wp_enable; return 0; }; @@ -963,6 +971,13 @@ static int fsl_esdhc_probe(struct udevice *dev) &priv->cd_gpio, GPIOD_IS_IN); } + priv->wp_enable = 1; + + ret = gpio_request_by_name_nodev(fdt, node, "wp-gpios", 0, + &priv->wp_gpio, GPIOD_IS_IN); + if (ret) + priv->wp_enable = 0; + /* * TODO: * Because lack of clk driver, if SDHC clk is not enabled, diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 78c67c880a..c6f46664c7 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -177,6 +177,7 @@ struct fsl_esdhc_cfg { phys_addr_t esdhc_base; u32 sdhc_clk; u8 max_bus_width; + u8 wp_enable; struct mmc_config cfg; };