From: Patrick Delaunay <patrick.delaunay@st.com>
Date: Wed, 10 Apr 2019 12:09:22 +0000 (+0200)
Subject: stm32mp1: ram: increase the delay after reset to 128 cycles
X-Git-Tag: v2025.01-rc5-pxa1908~2962^2~7
X-Git-Url: http://git.dujemihanovic.xyz/img/static/git-logo.png?a=commitdiff_plain;h=0cb1aa94093c22dd5b3dce32d371e154abc06ffe;p=u-boot.git
stm32mp1: ram: increase the delay after reset to 128 cycles
Component Notification DDR controller errata (3.00a):9001313030
Synchronization Time Waited After De-assertion of presetn is
128 pclk Cycles.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
---
diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c
index caa7813d44..82003667de 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ddr.c
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c
@@ -401,11 +401,9 @@ void stm32mp1_ddr_init(struct ddr_info *priv,
*/
clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
-/* 1.4. wait 4 cycles for synchronization */
- asm(" nop");
- asm(" nop");
- asm(" nop");
- asm(" nop");
+/* 1.4. wait 128 cycles to permit initialization of end logic */
+ udelay(2);
+ /* for PCLK = 133MHz => 1 us is enough, 2 to allow lower frequency */
/* 1.5. initialize registers ddr_umctl2 */
/* Stop uMCTL2 before PHY is ready */