]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
dm: arm64: ls1043a: add i2c DM support
authorBiwen Li <biwen.li@nxp.com>
Wed, 5 Feb 2020 14:02:16 +0000 (22:02 +0800)
committerPriyanka Jain <priyanka.jain@nxp.com>
Mon, 30 Mar 2020 02:42:13 +0000 (08:12 +0530)
This supports i2c DM and enables CONFIG_DM_I2C
for SoC LS1043A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
21 files changed:
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
arch/arm/include/asm/gpio.h
board/freescale/ls1043aqds/ls1043aqds.c
configs/ls1043aqds_defconfig
configs/ls1043aqds_lpuart_defconfig
configs/ls1043aqds_nand_defconfig
configs/ls1043aqds_nor_ddr3_defconfig
configs/ls1043aqds_qspi_defconfig
configs/ls1043aqds_sdcard_ifc_defconfig
configs/ls1043aqds_sdcard_qspi_defconfig
configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
configs/ls1043aqds_tfa_defconfig
configs/ls1043ardb_SECURE_BOOT_defconfig
configs/ls1043ardb_defconfig
configs/ls1043ardb_nand_SECURE_BOOT_defconfig
configs/ls1043ardb_nand_defconfig
configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
configs/ls1043ardb_sdcard_defconfig
configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
configs/ls1043ardb_tfa_defconfig
include/configs/ls1043a_common.h

index 275c66d99291686798405a464fb0e62ebb5e718f..760053e401229a3ad31b7cb332205e9ff4bb70aa 100644 (file)
@@ -74,11 +74,11 @@ config ARCH_LS1043A
        select SYS_FSL_HAS_DDR4
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
-       select SYS_I2C_MXC
-       select SYS_I2C_MXC_I2C1
-       select SYS_I2C_MXC_I2C2
-       select SYS_I2C_MXC_I2C3
-       select SYS_I2C_MXC_I2C4
+       select SYS_I2C_MXC if !DM_I2C
+       select SYS_I2C_MXC_I2C1 if !DM_I2C
+       select SYS_I2C_MXC_I2C2 if !DM_I2C
+       select SYS_I2C_MXC_I2C3 if !DM_I2C
+       select SYS_I2C_MXC_I2C4 if !DM_I2C
        imply CMD_PCI
 
 config ARCH_LS1046A
index 84e5cb46e5a9de9079859f4163e74300878d46b4..5d6b269deda5089b364a6fc24502a49ce1d4474d 100644 (file)
@@ -4,7 +4,8 @@
        !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_LX2160A) && \
        !defined(CONFIG_ARCH_LS1028A) && !defined(CONFIG_ARCH_LS2080A) && \
        !defined(CONFIG_ARCH_LS1088A) && !defined(CONFIG_ARCH_ASPEED) && \
-       !defined(CONFIG_ARCH_LS1012A) && !defined(CONFIG_ARCH_U8500) && \
+       !defined(CONFIG_ARCH_LS1012A) && !defined(CONFIG_ARCH_LS1043A) && \
+       !defined(CONFIG_ARCH_U8500) && \
        !defined(CONFIG_CORTINA_PLATFORM)
 #include <asm/arch/gpio.h>
 #endif
index 8c96b962b7883279793cb66e1d0167e883a5e74f..2d4b18cdbcb56a9e8f35bcaa50bc13b5c578e422 100644 (file)
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
  */
 
 #include <common.h>
@@ -271,11 +272,24 @@ unsigned long get_board_ddr_clk(void)
        return 66666666;
 }
 
-int select_i2c_ch_pca9547(u8 ch)
+int select_i2c_ch_pca9547(u8 ch, int bus_num)
 {
        int ret;
 
+#ifdef CONFIG_DM_I2C
+       struct udevice *dev;
+
+       ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
+                                     1, &dev);
+       if (ret) {
+               printf("%s: Cannot find udev for a bus %d\n", __func__,
+                      bus_num);
+               return ret;
+       }
+       ret = dm_i2c_write(dev, 0, &ch, 1);
+#else
        ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#endif
        if (ret) {
                puts("PCA: failed to select proper channel\n");
                return ret;
@@ -290,8 +304,10 @@ int dram_init(void)
         * When resuming from deep sleep, the I2C channel may not be
         * in the default channel. So, switch to the default channel
         * before accessing DDR SPD.
+        *
+        * PCA9547 mount on I2C1 bus
         */
-       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
        fsl_initdram();
 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
        defined(CONFIG_SPL_BUILD)
@@ -304,16 +320,83 @@ int dram_init(void)
 
 int i2c_multiplexer_select_vid_channel(u8 channel)
 {
-       return select_i2c_ch_pca9547(channel);
+       return select_i2c_ch_pca9547(channel, 0);
 }
 
 void board_retimer_init(void)
 {
        u8 reg;
+       int bus_num = 0;
 
        /* Retimer is connected to I2C1_CH7_CH5 */
-       select_i2c_ch_pca9547(I2C_MUX_CH7);
+       select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num);
        reg = I2C_MUX_CH5;
+#ifdef CONFIG_DM_I2C
+       struct udevice *dev;
+       int ret;
+
+       ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
+                                     1, &dev);
+       if (ret) {
+               printf("%s: Cannot find udev for a bus %d\n", __func__,
+                      bus_num);
+               return;
+       }
+       dm_i2c_write(dev, 0, &reg, 1);
+
+       /* Access to Control/Shared register */
+       ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
+                                     1, &dev);
+       if (ret) {
+               printf("%s: Cannot find udev for a bus %d\n", __func__,
+                      bus_num);
+               return;
+       }
+
+       reg = 0x0;
+       dm_i2c_write(dev, 0xff, &reg, 1);
+
+       /* Read device revision and ID */
+       dm_i2c_read(dev, 1, &reg, 1);
+       debug("Retimer version id = 0x%x\n", reg);
+
+       /* Enable Broadcast. All writes target all channel register sets */
+       reg = 0x0c;
+       dm_i2c_write(dev, 0xff, &reg, 1);
+
+       /* Reset Channel Registers */
+       dm_i2c_read(dev, 0, &reg, 1);
+       reg |= 0x4;
+       dm_i2c_write(dev, 0, &reg, 1);
+
+       /* Enable override divider select and Enable Override Output Mux */
+       dm_i2c_read(dev, 9, &reg, 1);
+       reg |= 0x24;
+       dm_i2c_write(dev, 9, &reg, 1);
+
+       /* Select VCO Divider to full rate (000) */
+       dm_i2c_read(dev, 0x18, &reg, 1);
+       reg &= 0x8f;
+       dm_i2c_write(dev, 0x18, &reg, 1);
+
+       /* Selects active PFD MUX Input as Re-timed Data (001) */
+       dm_i2c_read(dev, 0x1e, &reg, 1);
+       reg &= 0x3f;
+       reg |= 0x20;
+       dm_i2c_write(dev, 0x1e, &reg, 1);
+
+       /* Set data rate as 10.3125 Gbps */
+       reg = 0x0;
+       dm_i2c_write(dev, 0x60, &reg, 1);
+       reg = 0xb2;
+       dm_i2c_write(dev, 0x61, &reg, 1);
+       reg = 0x90;
+       dm_i2c_write(dev, 0x62, &reg, 1);
+       reg = 0xb3;
+       dm_i2c_write(dev, 0x63, &reg, 1);
+       reg = 0xcd;
+       dm_i2c_write(dev, 0x64, &reg, 1);
+#else
        i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
 
        /* Access to Control/Shared register */
@@ -360,9 +443,10 @@ void board_retimer_init(void)
        i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
        reg = 0xcd;
        i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
+#endif
 
        /* Return the default channel */
-       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num);
 }
 
 int board_early_init_f(void)
@@ -375,8 +459,10 @@ int board_early_init_f(void)
        u8 uart;
 #endif
 
+#ifdef CONFIG_SYS_I2C
 #ifdef CONFIG_SYS_I2C_EARLY_INIT
        i2c_early_init_f();
+#endif
 #endif
        fsl_lsch2_early_init_f();
 
@@ -457,7 +543,7 @@ int board_init(void)
        erratum_a010315();
 #endif
 
-       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
        board_retimer_init();
 
 #ifdef CONFIG_SYS_FSL_SERDES
index 2885552ef34fec40eedcdf42337ee6f99ad3559b..93b86af6074e330a20560c85fed20257fa4d1cb1 100644 (file)
@@ -62,3 +62,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
index 9d9229ac03a9d9097449a169f4c0573e1d57e733..f89c2ee3a4fb4c1878677bf28cd633e5f0f88308 100644 (file)
@@ -64,3 +64,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
index c45eaea02a50dbfca0eaeb4d2ae3539f81ef29f0..a169bfef8f646c4fbf65fa89f6178f0b0a602c2a 100644 (file)
@@ -78,3 +78,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
index 8d28fe1baff692f7225cd9de1dadd5c99f0f53da..01d0af30b1774c60fa435e085c49c252d794a063 100644 (file)
@@ -63,3 +63,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
index 86b2eb56b84bfb115c5242c0da300a3cfed383f5..65eff7c40b839d0dfa757a8626f056654f35ceb5 100644 (file)
@@ -58,3 +58,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
index bf3f0d09909dedf350e5ec52839a7be5aaea56f5..c5042a345d7da93190b7f342ab29d420b9903138 100644 (file)
@@ -79,3 +79,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
index 0449469b895148861f592119397746cb1e9fadd1..12706a48dc88926d24286124fe4657fb3320f68b 100644 (file)
@@ -72,3 +72,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
index 0ece698350d02c522d7e0afb648282df7e017707..b7335bcd3352cf0ca0e3ea335ca814629e235f16 100644 (file)
@@ -63,3 +63,5 @@ CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
index 24db72a39d2b715b1ba14f5d1d549667a88a3364..6e594ed07c6721344f1ee40b03bd6e63cd46c760 100644 (file)
@@ -71,3 +71,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
index 5e030e2586dbc99eb7d95550179f68309977ccb9..153a62866ffe9fe6f8fd33af5f4b2cbc93ec6c68 100644 (file)
@@ -55,3 +55,5 @@ CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
index 0676cbccdd6bad811f055c514d1389ce13b3d44f..d1e534388b9dc4e423465d7da4eebcf35fc1a99f 100644 (file)
@@ -55,3 +55,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
index 1f4c5705d58be4c43a828770a986236b6cc193a5..252c7c8313af7ef13c97aea1549054c12fc8da99 100644 (file)
@@ -75,3 +75,5 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
index e7fe2de309f663e578d68c9dffca0150d1e6b0d9..de18aaa0635c84d617093bbabaa9f6105f33ef8f 100644 (file)
@@ -74,3 +74,5 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
index 6529c7334c1cc0af83b5845be1897a97326ca892..149b25ffe5291b0a619251843fa1781e7d762bfe 100644 (file)
@@ -74,3 +74,5 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
index 228262477cd74567c434f864b85d6b0bfce0dc53..b386fc668ccfd1bf072d80475bd27cd3a5fb75b8 100644 (file)
@@ -73,3 +73,5 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
index 94ca502f3b5721438f60f7b7e8e544b1a560800a..36eb0fcff72dda2ea0f01961eb00a9fe514e5dce 100644 (file)
@@ -56,3 +56,5 @@ CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
index 4154075986cba903f6908f2c895f30f34a8bea12..eaddbca79f8bd4f860635147a26a35f2404f6dbe 100644 (file)
@@ -59,3 +59,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
index bf24d4036d2a0b809cc226b5491ce3b2df2f9b3e..985f40412c679d5c54a1390a46ce4c5ed1a66138 100644 (file)
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2015 Freescale Semiconductor
+ * Copyright (C) 2019 NXP
  */
 
 #ifndef __LS1043A_COMMON_H
 #endif
 
 /* I2C */
+#ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_MXC_I2C4                /* enable I2C bus 4 */
+#else
+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
+#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
+#endif
 
 /* PCIe */
 #ifndef SPL_NO_PCIE