riscv: Add Kconfig to support RISC-V

Add Kconfig and makefile for RISC-V
Also modify MAINTAINERS for it.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>

diff --git a/MAINTAINERS b/MAINTAINERS
index 9b4b63b063d0b653d8b4f6d856250f5e4f1fd0e4..754db5553d467b9e69704da90799b52bd83adada 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -423,6 +423,13 @@ S: Orphaned (Since 2017-01)
 T:     git git://git.denx.de/u-boot-onenand.git
 F:     drivers/mtd/onenand/
 
+RISC-V
+M:     Rick Chen <rick@andestech.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-riscv.git
+F:     arch/riscv/
+F:     tools/prelink-riscv.c
+
 SANDBOX
 M:     Simon Glass <sjg@chromium.org>
 S:     Maintained

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
new file mode 100644 (file)
index 0000000..c50be37
--- /dev/null
+++ b/arch/riscv/Kconfig
@@ -0,0 +1,42 @@
+menu "RISCV architecture"
+       depends on RISCV
+
+config SYS_ARCH
+       default "riscv"
+
+choice
+       prompt "Target select"
+       optional
+
+config TARGET_NX25_AE250
+       bool "Support nx25-ae250"
+
+endchoice
+
+source "board/AndesTech/nx25-ae250/Kconfig"
+
+choice
+       prompt "CPU selection"
+       default CPU_RISCV_32
+
+config CPU_RISCV_32
+       bool "RISCV 32 bit"
+       select 32BIT
+       help
+         Choose this option to build an U-Boot for RISCV32 architecture.
+
+config CPU_RISCV_64
+       bool "RISCV 64 bit"
+       select 64BIT
+       help
+         Choose this option to build an U-Boot for RISCV64 architecture.
+
+endchoice
+
+config 32BIT
+       bool
+
+config 64BIT
+       bool
+
+endmenu

diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
new file mode 100644 (file)
index 0000000..09d24db
--- /dev/null
+++ b/arch/riscv/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright (C) 2017 Andes Technology Corporation.
+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+head-y := arch/riscv/cpu/$(CPU)/start.o
+
+libs-y += arch/riscv/cpu/$(CPU)/
+libs-y += arch/riscv/lib/

diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk
new file mode 100644 (file)
index 0000000..6b681c4
--- /dev/null
+++ b/arch/riscv/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (c) 2017 Microsemi Corporation.
+# Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
+#
+# Copyright (C) 2017 Andes Technology Corporation
+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := riscv32-unknown-linux-gnu-
+endif
+
+32bit-emul             := elf32lriscv
+64bit-emul             := elf64lriscv
+
+ifdef CONFIG_32BIT
+PLATFORM_LDFLAGS       += -m $(32bit-emul)
+endif
+
+ifdef CONFIG_64BIT
+PLATFORM_LDFLAGS       += -m $(64bit-emul)
+endif
+
+CONFIG_STANDALONE_LOAD_ADDR = 0x00000000 \
+                             -T $(srctree)/examples/standalone/riscv.lds
+
+PLATFORM_CPPFLAGS      += -ffixed-gp -fpic
+PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -gdwarf-2
+LDFLAGS_u-boot += --gc-sections -static -pie