powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2

Chassis generation 2 has different mask and shift. Use macro instead of
magic numbers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 203f53d60032946b1960cf2881f3cb2c139a8665..6c2bc34714bc39da56f6d5ac52d00017e978475e 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -85,7 +85,9 @@ void get_sys_info (sys_info_t * sysInfo)
        sysInfo->freqDDRBus = sysclk;
 
        sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
-       mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f;
+       mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
+                       FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
+                       & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
        if (mem_pll_rat > 2)
                sysInfo->freqDDRBus *= mem_pll_rat;
        else

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 1181d2b93c23bde1686a8a4183c782a4d0115ea2..d0824b36e5782b80b55afb52597254d53da839c4 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1757,6 +1757,13 @@ typedef struct ccsr_gur {
        u32     brrl;           /* Boot release */
        u8      res17[24];
        u32     rcwsr[16];      /* Reset control word status */
+#ifndef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT   17
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK    0x1f
+#else
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT   16
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK    0x3f
+#endif
 #define FSL_CORENET_RCWSR4_SRDS_PRTCL          0xfc000000
 #define FSL_CORENET_RCWSR5_DDR_SYNC            0x00000080
 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT               7