--- /dev/null
+/*
+ * (C) Copyright 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on da830evm.c. Original Copyrights follow:
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/da850_lowlevel.h>
+#include <asm/arch/davinci_misc.h>
+#include <asm/arch/emif_defs.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sdmmc_defs.h>
+#include <asm/arch/timer_defs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct lpsc_resource lpsc[] = {
+ { DAVINCI_LPSC_AEMIF },
+ { DAVINCI_LPSC_SPI1 },
+ { DAVINCI_LPSC_ARM_RAM_ROM },
+ { DAVINCI_LPSC_UART0 },
+ { DAVINCI_LPSC_EMAC },
+ { DAVINCI_LPSC_UART0 },
+ { DAVINCI_LPSC_GPIO },
+ { DAVINCI_LPSC_DDR_EMIF },
+ { DAVINCI_LPSC_UART1 },
+ { DAVINCI_LPSC_UART2 },
+ { DAVINCI_LPSC_MMC_SD1 },
+ { DAVINCI_LPSC_USB20 },
+ { DAVINCI_LPSC_USB11 },
+};
+
+static const struct pinmux_config enbw_pins[] = {
+ { pinmux(0), 8, 0 },
+ { pinmux(0), 8, 1 },
+ { pinmux(0), 8, 2 },
+ { pinmux(0), 8, 3 },
+ { pinmux(0), 8, 4 },
+ { pinmux(0), 8, 5 },
+ { pinmux(1), 4, 0 },
+ { pinmux(1), 8, 1 },
+ { pinmux(1), 8, 2 },
+ { pinmux(1), 8, 3 },
+ { pinmux(1), 8, 4 },
+ { pinmux(1), 8, 5 },
+ { pinmux(1), 8, 6 },
+ { pinmux(1), 4, 7 },
+ { pinmux(2), 8, 0 },
+ { pinmux(5), 1, 0 },
+ { pinmux(5), 1, 3 },
+ { pinmux(5), 1, 7 },
+ { pinmux(6), 1, 0 },
+ { pinmux(6), 1, 1 },
+ { pinmux(6), 8, 2 },
+ { pinmux(6), 8, 3 },
+ { pinmux(6), 1, 4 },
+ { pinmux(6), 8, 5 },
+ { pinmux(6), 1, 7 },
+ { pinmux(7), 8, 2 },
+ { pinmux(7), 1, 3 },
+ { pinmux(7), 1, 6 },
+ { pinmux(7), 1, 7 },
+ { pinmux(13), 8, 2 },
+ { pinmux(13), 8, 3 },
+ { pinmux(13), 8, 4 },
+ { pinmux(13), 8, 5 },
+ { pinmux(13), 8, 6 },
+ { pinmux(13), 8, 7 },
+ { pinmux(14), 8, 0 },
+ { pinmux(14), 8, 1 },
+ { pinmux(16), 8, 1 },
+ { pinmux(16), 8, 2 },
+ { pinmux(16), 8, 3 },
+ { pinmux(16), 8, 4 },
+ { pinmux(16), 8, 5 },
+ { pinmux(16), 8, 6 },
+ { pinmux(16), 8, 7 },
+ { pinmux(17), 1, 0 },
+ { pinmux(17), 1, 1 },
+ { pinmux(17), 1, 2 },
+ { pinmux(17), 8, 3 },
+ { pinmux(17), 8, 4 },
+ { pinmux(17), 8, 5 },
+ { pinmux(17), 8, 6 },
+ { pinmux(17), 8, 7 },
+ { pinmux(18), 8, 0 },
+ { pinmux(18), 8, 1 },
+ { pinmux(18), 2, 2 },
+ { pinmux(18), 2, 3 },
+ { pinmux(18), 2, 4 },
+ { pinmux(18), 8, 6 },
+ { pinmux(18), 8, 7 },
+ { pinmux(19), 8, 0 },
+ { pinmux(19), 2, 1 },
+ { pinmux(19), 2, 2 },
+ { pinmux(19), 2, 3 },
+ { pinmux(19), 2, 4 },
+ { pinmux(19), 8, 5 },
+ { pinmux(19), 8, 6 },
+};
+
+const struct pinmux_resource pinmuxes[] = {
+ PINMUX_ITEM(emac_pins_mii),
+ PINMUX_ITEM(emac_pins_mdio),
+ PINMUX_ITEM(i2c0_pins),
+ PINMUX_ITEM(emifa_pins_cs2),
+ PINMUX_ITEM(emifa_pins_cs3),
+ PINMUX_ITEM(emifa_pins_cs4),
+ PINMUX_ITEM(emifa_pins_nand),
+ PINMUX_ITEM(emifa_pins_nor),
+ PINMUX_ITEM(spi1_pins_base),
+ PINMUX_ITEM(spi1_pins_scs0),
+ PINMUX_ITEM(uart1_pins_txrx),
+ PINMUX_ITEM(uart2_pins_txrx),
+ PINMUX_ITEM(uart2_pins_rtscts),
+ PINMUX_ITEM(enbw_pins),
+};
+
+const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
+
+struct gpio_config {
+ char name[GPIO_NAME_SIZE];
+ unsigned char bank;
+ unsigned char gpio;
+ unsigned char out;
+ unsigned char value;
+};
+
+static const struct gpio_config enbw_gpio_config[] = {
+ { "RS485 enable", 8, 11, 1, 0 },
+ { "RS485 iso", 8, 10, 1, 0 },
+ { "W2HUT RS485 Rx ena", 8, 9, 1, 0 },
+ { "W2HUT RS485 iso", 8, 8, 1, 0 },
+ { "LAN reset", 7, 15, 1, 1 },
+ { "ena 11V PLC", 7, 14, 1, 0 },
+ { "ena 1.5V PLC", 7, 13, 1, 0 },
+ { "disable VBUS", 7, 12, 1, 1 },
+ { "PLC reset", 6, 13, 1, 1 },
+ { "LCM RS", 6, 12, 1, 0 },
+ { "LCM R/W", 6, 11, 1, 0 },
+ { "PLC pairing", 6, 10, 1, 1 },
+ { "PLC MDIO CLK", 6, 9, 1, 0 },
+ { "HK218", 6, 8, 1, 0 },
+ { "HK218 Rx", 6, 1, 1, 1 },
+ { "TPM reset", 6, 0, 1, 1 },
+ { "LCM E", 2, 2, 1, 1 },
+ { "PV-IF RxD ena", 0, 15, 1, 1 },
+ { "LED1", 1, 15, 1, 1 },
+ { "LED2", 0, 1, 1, 1 },
+ { "LED3", 0, 2, 1, 1 },
+ { "LED4", 0, 3, 1, 1 },
+ { "LED5", 0, 4, 1, 1 },
+ { "LED6", 0, 5, 1, 0 },
+ { "LED7", 0, 6, 1, 0 },
+ { "LED8", 0, 14, 1, 0 },
+ { "USER1", 0, 12, 0, 0 },
+ { "USER2", 0, 13, 0, 0 },
+};
+
+#define PHY_POWER 0x0800
+
+static void enbw_cmc_switch(int port, int on)
+{
+ const char *devname;
+ unsigned char phyaddr = 3;
+ unsigned char reg = 0;
+ unsigned short data;
+
+ if (port == 1)
+ phyaddr = 2;
+
+ devname = miiphy_get_current_dev();
+ if (!devname) {
+ printf("Error: no mii device\n");
+ return;
+ }
+ if (miiphy_read(devname, phyaddr, reg, &data) != 0) {
+ printf("Error reading from the PHY addr=%02x reg=%02x\n",
+ phyaddr, reg);
+ return;
+ }
+
+ if (on)
+ data &= ~PHY_POWER;
+ else
+ data |= PHY_POWER;
+
+ if (miiphy_write(devname, phyaddr, reg, data) != 0) {
+ printf("Error writing to the PHY addr=%02x reg=%02x\n",
+ phyaddr, reg);
+ return;
+ }
+}
+
+int board_init(void)
+{
+ int i, ret;
+
+#ifndef CONFIG_USE_IRQ
+ irq_init();
+#endif
+ /* address of boot parameters, not used as booting with DTT */
+ gd->bd->bi_boot_params = 0;
+
+ for (i = 0; i < ARRAY_SIZE(enbw_gpio_config); i++) {
+ int gpio = enbw_gpio_config[i].bank * 16 +
+ enbw_gpio_config[i].gpio;
+
+ ret = gpio_request(gpio, enbw_gpio_config[i].name);
+ if (ret) {
+ printf("%s: Could not get %s gpio\n", __func__,
+ enbw_gpio_config[i].name);
+ return -1;
+ }
+
+ if (enbw_gpio_config[i].out)
+ gpio_direction_output(gpio,
+ enbw_gpio_config[i].value);
+ else
+ gpio_direction_input(gpio);
+ }
+
+ /* setup the SUSPSRC for ARM to control emulation suspend */
+ clrbits_le32(&davinci_syscfg_regs->suspsrc,
+ (DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
+ DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
+ DAVINCI_SYSCFG_SUSPSRC_UART2));
+
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+/*
+ * Initializes on-board ethernet controllers.
+ */
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_DRIVER_TI_EMAC
+ davinci_emac_mii_mode_sel(0);
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+ if (!davinci_emac_initialize()) {
+ printf("Error: Ethernet init failed!\n");
+ return -1;
+ }
+
+ if (hwconfig_subarg_cmp("switch", "lan", "on"))
+ /* Switch port lan on */
+ enbw_cmc_switch(1, 1);
+ else
+ enbw_cmc_switch(1, 0);
+
+ if (hwconfig_subarg_cmp("switch", "pwl", "on"))
+ /* Switch port pwl on */
+ enbw_cmc_switch(2, 1);
+ else
+ enbw_cmc_switch(2, 0);
+
+ return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+#ifdef CONFIG_PREBOOT
+static uchar kbd_magic_prefix[] = "key_magic_";
+static uchar kbd_command_prefix[] = "key_cmd_";
+
+struct kbd_data_t {
+ char s1;
+};
+
+struct kbd_data_t *get_keys(struct kbd_data_t *kbd_data)
+{
+ /* read SW1 + SW2 */
+ kbd_data->s1 = gpio_get_value(12) +
+ (gpio_get_value(13) << 1);
+ return kbd_data;
+}
+
+static int compare_magic(const struct kbd_data_t *kbd_data, char *str)
+{
+ char s1 = str[0];
+
+ if (s1 >= '0' && s1 <= '9')
+ s1 -= '0';
+ else if (s1 >= 'a' && s1 <= 'f')
+ s1 = s1 - 'a' + 10;
+ else if (s1 >= 'A' && s1 <= 'F')
+ s1 = s1 - 'A' + 10;
+ else
+ return -1;
+
+ if (s1 != kbd_data->s1)
+ return -1;
+
+ return 0;
+}
+
+static char *key_match(const struct kbd_data_t *kbd_data)
+{
+ char magic[sizeof(kbd_magic_prefix) + 1];
+ char *suffix;
+ char *kbd_magic_keys;
+
+ /*
+ * The following string defines the characters that can be appended
+ * to "key_magic" to form the names of environment variables that
+ * hold "magic" key codes, i. e. such key codes that can cause
+ * pre-boot actions. If the string is empty (""), then only
+ * "key_magic" is checked (old behaviour); the string "125" causes
+ * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+ */
+ kbd_magic_keys = getenv("magic_keys");
+ if (kbd_magic_keys == NULL)
+ kbd_magic_keys = "";
+
+ /*
+ * loop over all magic keys;
+ * use '\0' suffix in case of empty string
+ */
+ for (suffix = kbd_magic_keys; *suffix ||
+ suffix == kbd_magic_keys; ++suffix) {
+ sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
+
+ if (compare_magic(kbd_data, getenv(magic)) == 0) {
+ char cmd_name[sizeof(kbd_command_prefix) + 1];
+ char *cmd;
+
+ sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
+ cmd = getenv(cmd_name);
+
+ return cmd;
+ }
+ }
+
+ return NULL;
+}
+#endif /* CONFIG_PREBOOT */
+
+int misc_init_r(void)
+{
+ char *s, buf[32];
+#ifdef CONFIG_PREBOOT
+ struct kbd_data_t kbd_data;
+ /* Decode keys */
+ char *str = strdup(key_match(get_keys(&kbd_data)));
+ /* Set or delete definition */
+ setenv("preboot", str);
+ free(str);
+#endif /* CONFIG_PREBOOT */
+
+ /* count all restarts, and save this in an environment var */
+ s = getenv("restartcount");
+
+ if (s)
+ sprintf(buf, "%ld", simple_strtoul(s, NULL, 10) + 1);
+ else
+ strcpy(buf, "1");
+
+ setenv("restartcount", buf);
+ saveenv();
+
+#ifdef CONFIG_HW_WATCHDOG
+ davinci_hw_watchdog_enable();
+#endif
+
+ return 0;
+}
+
+struct cmc_led {
+ char name[20];
+ unsigned char bank;
+ unsigned char gpio;
+};
+
+struct cmc_led led_table[] = {
+ {"led1", 1, 15},
+ {"led2", 0, 1},
+ {"led3", 0, 2},
+ {"led4", 0, 3},
+ {"led5", 0, 4},
+ {"led6", 0, 5},
+ {"led7", 0, 6},
+ {"led8", 0, 14},
+};
+
+static int cmc_get_led_state(struct cmc_led *led)
+{
+ int value;
+ int gpio = led->bank * 16 + led->gpio;
+
+ value = gpio_get_value(gpio);
+
+ return value;
+}
+
+static int cmc_set_led_state(struct cmc_led *led, int state)
+{
+ int gpio = led->bank * 16 + led->gpio;
+
+ gpio_set_value(gpio, state);
+ return 0;
+}
+
+static int do_led(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ struct cmc_led *led;
+ int found = 0;
+ int i = 0;
+ int only_print = 0;
+ int len = ARRAY_SIZE(led_table);
+
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ if (argc < 3)
+ only_print = 1;
+
+ led = led_table;
+ while ((!found) && (i < len)) {
+ if (strcmp(argv[1], led->name) == 0) {
+ found = 1;
+ } else {
+ led++;
+ i++;
+ }
+ }
+ if (!found)
+ return cmd_usage(cmdtp);
+
+ if (only_print) {
+ if (cmc_get_led_state(led))
+ printf("on\n");
+ else
+ printf("off\n");
+
+ return 0;
+ }
+ if (strcmp(argv[2], "on") == 0)
+ cmc_set_led_state(led, 1);
+ else
+ cmc_set_led_state(led, 0);
+
+ return 0;
+}
+
+U_BOOT_CMD(led, 3, 1, do_led,
+ "switch on/off board led",
+ "[name] [on/off]"
+);
+
+#ifdef CONFIG_HW_WATCHDOG
+void hw_watchdog_reset(void)
+{
+ davinci_hw_watchdog_reset();
+}
+#endif
+
+#if defined(CONFIG_POST)
+void arch_memory_failure_handle(void)
+{
+ struct davinci_gpio *gpio = davinci_gpio_bank01;
+ int state = 1;
+
+ /*
+ * if memor< failure blink with the LED 1,2 and 3
+ * as we running from flash, we cannot use the gpio
+ * api here, so access the gpio pin direct through
+ * the gpio register.
+ */
+ while (1) {
+ if (state) {
+ clrbits_le32(&gpio->out_data, 0x80000006);
+ state = 0;
+ } else {
+ setbits_le32(&gpio->out_data, 0x80000006);
+ state = 1;
+ }
+ udelay(500);
+ }
+}
+#endif
+
+#if defined(CONFIG_BOOTCOUNT_LIMIT)
+void bootcount_store(ulong a)
+{
+ struct davinci_rtc *reg =
+ (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR;
+
+ /*
+ * write RTC kick register to enable write
+ * for RTC Scratch registers. Cratch0 and 1 are
+ * used for bootcount values.
+ */
+ out_be32(®->kick0r, RTC_KICK0R_WE);
+ out_be32(®->kick1r, RTC_KICK1R_WE);
+ out_be32(®->scratch0, a);
+ out_be32(®->scratch1, BOOTCOUNT_MAGIC);
+}
+
+ulong bootcount_load(void)
+{
+ struct davinci_rtc *reg =
+ (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR;
+
+ if (in_be32(®->scratch1) != BOOTCOUNT_MAGIC)
+ return 0;
+ else
+ return in_be32(®->scratch0);
+}
+#endif
+
+void board_gpio_init(void)
+{
+ struct davinci_gpio *gpio = davinci_gpio_bank01;
+
+ /*
+ * Power on required peripherals
+ * ARM does not have access by default to PSC0 and PSC1
+ * assuming here that the DSP bootloader has set the IOPU
+ * such that PSC access is available to ARM
+ */
+ if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
+ return;
+
+ /*
+ * set LED (gpio Interface not usable here)
+ * set LED pins to output and state 0
+ */
+ clrbits_le32(&gpio->dir, 0x8000407e);
+ clrbits_le32(&gpio->out_data, 0x8000407e);
+ /* set LED 1 - 5 to state on */
+ setbits_le32(&gpio->out_data, 0x8000001e);
+}
+
+int board_late_init(void)
+{
+ cmc_set_led_state(&led_table[4], 0);
+
+ return 0;
+}
+
+void show_boot_progress(int val)
+{
+ switch (val) {
+ case 1:
+ cmc_set_led_state(&led_table[4], 1);
+ break;
+ case 4:
+ cmc_set_led_state(&led_table[4], 0);
+ break;
+ case 15:
+ cmc_set_led_state(&led_table[4], 1);
+ break;
+ }
+}
+
+#ifdef CONFIG_DAVINCI_MMC
+static struct davinci_mmc mmc_sd1 = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
+ .input_clk = 228000000,
+ .host_caps = MMC_MODE_4BIT,
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .version = MMC_CTLR_VERSION_2,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ mmc_sd1.input_clk = clk_get(DAVINCI_MMC_CLKID);
+ /* Add slot-0 to mmc subsystem */
+ return davinci_mmc_init(bis, &mmc_sd1);
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 7
+#define CONFIG_USE_NAND
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
+#define CONFIG_SOC_DA850 /* TI DA850 SoC */
+#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ 24000000
+#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_DA850_LOWLEVEL
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DA8XX_GPIO
+#define CONFIG_HOSTNAME enbw_cmc
+#define CONFIG_DISPLAY_CPUINFO
+
+#define MACH_TYPE_ENBW_CMC 3585
+#define CONFIG_MACH_TYPE MACH_TYPE_ENBW_CMC
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
+#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
+
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
+#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_DA850_LPSC_UART DAVINCI_LPSC_UART2
+/*
+ * I2C Configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED 80000
+#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
+#define CONFIG_CMD_I2C
+
+#define CONFIG_CMD_DTT
+#define CONFIG_DTT_LM75
+#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
+#define CONFIG_SYS_DTT_MAX_TEMP 70
+#define CONFIG_SYS_DTT_LOW_TEMP -30
+#define CONFIG_SYS_DTT_HYSTERESIS 3
+
+/*
+ * Flash & Environment
+ */
+#ifdef CONFIG_USE_NAND
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_NAND_CS 3
+#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_SYS_CLE_MASK 0x10
+#define CONFIG_SYS_ALE_MASK 0x8
+#undef CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+
+#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=davinci_nand.1"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=" \
+ "physmap-flash.0:" \
+ "512k(U-Boot)," \
+ "64k(env1)," \
+ "64k(env2)," \
+ "-(rest);" \
+ "davinci_nand.1:" \
+ "128k(dtb)," \
+ "3m(kernel)," \
+ "4m(rootfs)," \
+ "-(userfs)"
+
+
+#define CONFIG_CMD_MTDPARTS
+
+#endif
+
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+#endif
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_SYS_FLASH_BASE 0x60000000
+#define CONFIG_SYS_FLASH_SIZE 0x01000000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+#define CONFIG_FLASH_16BIT /* Flash is 16-bit */
+
+#define CONFIG_CMD_FLASH
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_SYS_MONITOR_LEN 0x80000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE (64 << 10)
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
+ CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+#undef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_DEFAULT_SETTINGS_ADDR (CONFIG_ENV_ADDR_REDUND + \
+ CONFIG_ENV_SECT_SIZE)
+
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "u-boot_addr_r=c0000000\0" \
+ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
+ "update=protect off " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize};"\
+ "erase " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
+ "cp.b ${u-boot_addr_r} " xstr(CONFIG_SYS_FLASH_BASE) \
+ " ${filesize};" \
+ "protect on " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize}\0"\
+ "netdev=eth0\0" \
+ "rootpath=/opt/eldk-arm/arm\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "kernel_addr_r=c0700000\0" \
+ "fdt_addr_r=c0600000\0" \
+ "ramdisk_addr_r=c0b00000\0" \
+ "fdt_file=" xstr(CONFIG_HOSTNAME) "/" \
+ xstr(CONFIG_HOSTNAME) ".dtb\0" \
+ "kernel_file=" xstr(CONFIG_HOSTNAME) "/uImage \0" \
+ "nand_ld_ramdsk=nand read ${ramdisk_addr_r} 320000 400000\0" \
+ "nand_ld_kernel=nand read ${kernel_addr_r} 20000 300000\0" \
+ "nand_ld_fdt=nand read ${fdt_addr_r} 0 2000\0" \
+ "load_kernel=tftp ${kernel_addr_r} ${kernel_file}\0" \
+ "load_fdt=tftp ${fdt_addr_r} ${fdt_file}\0" \
+ "load_nand=run nand_ld_ramdsk nand_ld_kernel nand_ld_fdt\0" \
+ "addcon=setenv bootargs ${bootargs} console=ttyS2," \
+ "${baudrate}n8\0" \
+ "net_nfs=run load_fdt load_kernel; " \
+ "run nfsargs addip addcon addmtd addmisc;" \
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "nand_selfnand=run load_nand ramargs addip addcon addmisc;bootm "\
+ "${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
+ "bootcmd=run net_nfs\0" \
+ "machid=e01\0" \
+ "key_cmd_0=echo key: 0\0" \
+ "key_cmd_1=echo key: 1\0" \
+ "key_cmd_2=echo key: 2\0" \
+ "key_cmd_3=echo key: 3\0" \
+ "key_magic_0=0\0" \
+ "key_magic_1=1\0" \
+ "key_magic_2=2\0" \
+ "key_magic_3=3\0" \
+ "magic_keys=0123\0" \
+ "hwconfig=switch:lan=on,pwl=off\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addmisc=setenv bootargs ${bootargs} davinci_mmc.use_dma=0\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "logversion=2\0" \
+ "\0"
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT "=> " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_HWCONFIG
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_BOARD_LATE_INIT
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_CACHE
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_LZO
+#define CONFIG_RBTREE
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+#if !defined(CONFIG_USE_NAND) && \
+ !defined(CONFIG_USE_NOR) && \
+ !defined(CONFIG_USE_SPIFLASH)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE (16 << 10)
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ENV
+#endif
+
+#define CONFIG_SYS_TEXT_BASE 0x60000000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_SDRAM_BASE 0xc0000000
+#define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00)
+
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+ "echo"
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMC_RESET_PIN 0x04000000
+#define CONFIG_CMC_RESET_TIMEOUT 3
+
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
+#define CONFIG_SYS_WDT_PERIOD_LOW 0x0c000000
+#define CONFIG_SYS_WDT_PERIOD_HIGH 0x0
+
+#define CONFIG_CMD_DATE
+#define CONFIG_RTC_DAVINCI
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DAVINCI_MMC
+#define CONFIG_MMC_MBLOCK
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MMC
+
+
+/* FDT support */
+#define CONFIG_OF_LIBFDT
+
+/* LowLevel Init */
+/* PLL */
+#define CONFIG_SYS_DV_CLKMODE 0
+#define CONFIG_SYS_DA850_PLL0_POSTDIV 0
+#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
+#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
+#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 /* 150MHz */
+#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
+#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
+#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
+#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
+
+#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
+#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
+#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
+#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
+
+#define CONFIG_SYS_DA850_PLL0_PLLM 18 /* PLL0 -> 456 MHz */
+#define CONFIG_SYS_DA850_PLL1_PLLM 24 /* PLL1 -> 300 MHz */
+
+/* DDR RAM */
+#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
+ DV_DDR_PHY_EXT_STRBEN | \
+ (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDBCR (0 | \
+ (0 << DV_DDR_SDCR_DDR2TERM1_SHIFT) | \
+ (0 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
+ (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
+ (0x1 << DV_DDR_SDCR_DDREN_SHIFT) | \
+ (0x1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
+ (0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) | \
+ (0x1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
+ (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
+ (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
+ (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDBCR2 4 /* 13 row address bits */
+
+/*
+ * freq = 150MHz -> t = 7ns
+ */
+#define CONFIG_SYS_DA850_DDR2_SDTIMR (0 | \
+ (0x0d << DV_DDR_SDTMR1_RFC_SHIFT) | \
+ (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
+ (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
+ (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
+ (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
+ (7 << DV_DDR_SDTMR1_RC_SHIFT) | \
+ (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
+ (readl(&dv_ddr2_regs_ctrl->sdtimr) & 0x4) | /* Reserved */ \
+ ((2 - 1) << DV_DDR_SDTMR1_WTR_SHIFT))
+
+/*
+ * freq = 150MHz -> t=7ns
+ */
+#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (0 | \
+ (readl(&dv_ddr2_regs_ctrl->sdtimr2) & 0x80000000) | /* Reserved */ \
+ (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
+ (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
+ (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
+ (15 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
+ (27 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
+ (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
+ (2 << DV_DDR_SDTMR2_CKE_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000407
+#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
+#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
+ DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
+ DAVINCI_SYSCFG_SUSPSRC_UART2 | \
+ DAVINCI_SYSCFG_SUSPSRC_EMAC |\
+ DAVINCI_SYSCFG_SUSPSRC_I2C)
+
+#define CONFIG_SYS_DA850_CS2CFG (DAVINCI_ABCR_WSETUP(2) | \
+ DAVINCI_ABCR_WSTROBE(6) | \
+ DAVINCI_ABCR_WHOLD(1) | \
+ DAVINCI_ABCR_RSETUP(2) | \
+ DAVINCI_ABCR_RSTROBE(6) | \
+ DAVINCI_ABCR_RHOLD(1) | \
+ DAVINCI_ABCR_ASIZE_16BIT)
+
+#define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \
+ DAVINCI_ABCR_WSTROBE(2) | \
+ DAVINCI_ABCR_WHOLD(1) | \
+ DAVINCI_ABCR_RSETUP(1) | \
+ DAVINCI_ABCR_RSTROBE(6) | \
+ DAVINCI_ABCR_RHOLD(1) | \
+ DAVINCI_ABCR_ASIZE_8BIT)
+
+/*
+ * NOR Bootconfiguration word:
+ * Method: Direc boot
+ * EMIFA access mode: 16 Bit
+ */
+#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
+
+#define CONFIG_POST (CONFIG_SYS_POST_MEMORY)
+#define CONFIG_SYS_POST_WORD_ADDR 0x8001FFF0
+#define CONFIG_LOGBUFFER
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_SYS_BOOTCOUNT_ADDR DAVINCI_RTC_BASE
+
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xc0080000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x60004000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x70000
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+#endif /* __CONFIG_H */
projects / u-boot.git / commitdiff
