eth: mtk-eth: enable mt7629 sgmii mode support in mediatek eth driver

The sgmii mode init flow is almost the same for all mediatek SoC, the
only difference is the register offset(SGMSYS_GEN2_SPEED) is 0x2028
in the old chip(mt7622) but changed to 0x128 for the newer chip(mt7629
and the following chips).

Signed-off-by: MarkLee <Mark-MC.Lee@mediatek.com>

diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c
index a06a15772c9bdd726d1ace81629f3cb98c6062cb..5183c08e14cd125342377e722fc0fa2595e14b8b 100644 (file)
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -1094,7 +1094,8 @@ static int mtk_phy_probe(struct udevice *dev)
 static void mtk_sgmii_init(struct mtk_eth_priv *priv)
 {
        /* Set SGMII GEN2 speed(2.5G) */
-       clrsetbits_le32(priv->sgmii_base + SGMSYS_GEN2_SPEED,
+       clrsetbits_le32(priv->sgmii_base + ((priv->soc == SOC_MT7622) ?
+                       SGMSYS_GEN2_SPEED : SGMSYS_GEN2_SPEED_V2),
                        SGMSYS_SPEED_2500, SGMSYS_SPEED_2500);
 
        /* Disable SGMII AN */

diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h
index be74ac27eaf021fc28009bcea4e39a876e89d2a7..057ecfaabf8c9fa299882caea2a228b0f701e93a 100644 (file)
--- a/drivers/net/mtk_eth.h
+++ b/drivers/net/mtk_eth.h
@@ -46,6 +46,7 @@
 #define SGMII_PHYA_PWD                 BIT(4)
 
 #define SGMSYS_GEN2_SPEED              0x2028
+#define SGMSYS_GEN2_SPEED_V2           0x128
 #define SGMSYS_SPEED_2500              BIT(2)
 
 /* Frame Engine Registers */