ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPS

Bit[7-4] for both register seq2core and core2seq handshake in HPS are not
required for triggering DDR re-calibration or resetting EMIF. So, ignoring
these bits just for playing it safe.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>

diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h
index 7460f8c220d9958683a5e8420c92fa98105795a4..07a0f9f2ae9b2687737a1cbfc7ddf17033171ace 100644 (file)
--- a/drivers/ddr/altera/sdram_soc64.h
+++ b/drivers/ddr/altera/sdram_soc64.h
@@ -53,7 +53,7 @@ struct altera_sdram_plat {
 #define DDR_HMC_INTSTAT_DERRPENA_SET_MSK       BIT(1)
 #define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK     BIT(16)
 #define DDR_HMC_INTMODE_INTMODE_SET_MSK                BIT(0)
-#define DDR_HMC_RSTHANDSHAKE_MASK              0x000000ff
+#define DDR_HMC_RSTHANDSHAKE_MASK              0x0000000f
 #define DDR_HMC_CORE2SEQ_INT_REQ               0xF
 #define DDR_HMC_SEQ2CORE_INT_RESP_MASK         BIT(3)
 #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK                0x001f1f1f