ARM: mvebu: a38x: restore support for setting timing

This restores support for configuring the timing mode based on the
ddr_topology. This was originally implemented in commit 90bcc3d38d2b
("driver/ddr: Add support for setting timing in hws_topology_map") but
was removed as part of the upstream sync.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c
index 29f81cdccfd46ac46a81e256a8226de0c778dc28..da663cf1bb0cacff61478891ba7d8d1b301690a5 100644 (file)
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -214,7 +214,8 @@ static struct mv_ddr_topology_map board_topology_map_1g = {
            MV_DDR_DIE_CAP_4GBIT,                       /* mem_size */
            DDR_FREQ_800,               /* frequency */
            0, 0,                       /* cas_wl cas_l */
-           MV_DDR_TEMP_NORMAL} },      /* temperature */
+           MV_DDR_TEMP_NORMAL,         /* temperature */
+           MV_DDR_TIM_2T} },           /* timing */
        BUS_MASK_32BIT,                 /* Busses mask */
        MV_DDR_CFG_DEFAULT,             /* ddr configuration data source */
        { {0} },                        /* raw spd data */
@@ -235,7 +236,8 @@ static struct mv_ddr_topology_map board_topology_map_2g = {
            MV_DDR_DIE_CAP_8GBIT,                       /* mem_size */
            DDR_FREQ_800,               /* frequency */
            0, 0,                       /* cas_wl cas_l */
-           MV_DDR_TEMP_NORMAL} },      /* temperature */
+           MV_DDR_TEMP_NORMAL,         /* temperature */
+           MV_DDR_TIM_2T} },           /* timing */
        BUS_MASK_32BIT,                 /* Busses mask */
        MV_DDR_CFG_DEFAULT,             /* ddr configuration data source */
        { {0} },                        /* raw spd data */

diff --git a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
index e39dc75f92287f63a15424e9d88ce3ca580cace6..92d7ae77f07e70108c162d70cb48398c18596894 100644 (file)
--- a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
+++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
@@ -69,7 +69,8 @@ static struct mv_ddr_topology_map board_topology_map = {
            MV_DDR_DIE_CAP_2GBIT,       /* mem_size */
            DDR_FREQ_800,               /* frequency */
            0, 0,                       /* cas_wl cas_l */
-           MV_DDR_TEMP_LOW} },         /* temperature */
+           MV_DDR_TEMP_LOW,            /* temperature */
+           MV_DDR_TIM_DEFAULT} },      /* timing */
        BUS_MASK_32BIT,                 /* Busses mask */
        MV_DDR_CFG_DEFAULT,             /* ddr configuration data source */
        { {0} },                        /* raw spd data */

diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
index ee12ca68ec2a1f5ed1ec7895d27bd823d3760cdc..a8cfe8af0a889eee36444f1a8987b10ef6b18dd2 100644 (file)
--- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
+++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
@@ -90,7 +90,8 @@ static struct mv_ddr_topology_map board_topology_map = {
            MV_DDR_DIE_CAP_4GBIT,       /* mem_size */
            DDR_FREQ_800,               /* frequency */
            0, 0,                       /* cas_wl cas_l */
-           MV_DDR_TEMP_LOW} },         /* temperature */
+           MV_DDR_TEMP_LOW,            /* temperature */
+           MV_DDR_TIM_DEFAULT} },      /* timing */
        BUS_MASK_32BIT,                 /* Busses mask */
        MV_DDR_CFG_DEFAULT,             /* ddr configuration data source */
        { {0} },                        /* raw spd data */

diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c
index f750e47b72283f426e0967b5b25ed9b20f1dffe8..320bc100c9dafba0f9db4267117e6a25e90f363d 100644 (file)
--- a/board/gdsys/a38x/controlcenterdc.c
+++ b/board/gdsys/a38x/controlcenterdc.c
@@ -53,7 +53,8 @@ static struct mv_ddr_topology_map ddr_topology_map = {
            MV_DDR_DIE_CAP_4GBIT,       /* mem_size */
            DDR_FREQ_533,               /* frequency */
            0, 0,                       /* cas_wl cas_l */
-           MV_DDR_TEMP_LOW} },         /* temperature */
+           MV_DDR_TEMP_LOW,            /* temperature */
+           MV_DDR_TIM_DEFAULT} },      /* timing */
        BUS_MASK_32BIT,                 /* Busses mask */
        MV_DDR_CFG_DEFAULT,             /* ddr configuration data source */
        { {0} },                        /* raw spd data */

diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c
index cc11feb85e30273c4ea002058a548a23adb7002f..ede303d4ebf96aaa4ac5946d40d1916876b1d506 100644 (file)
--- a/board/solidrun/clearfog/clearfog.c
+++ b/board/solidrun/clearfog/clearfog.c
@@ -83,7 +83,8 @@ static struct mv_ddr_topology_map board_topology_map = {
            MV_DDR_DIE_CAP_4GBIT,       /* mem_size */
            DDR_FREQ_800,               /* frequency */
            0, 0,                       /* cas_wl cas_l */
-           MV_DDR_TEMP_LOW} },         /* temperature */
+           MV_DDR_TEMP_LOW,            /* temperature */
+           MV_DDR_TIM_DEFAULT} },      /* timing */
        BUS_MASK_32BIT,                 /* Busses mask */
        MV_DDR_CFG_DEFAULT,             /* ddr configuration data source */
        { {0} },                        /* raw spd data */

diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c
index 1f26d506da3a9425343e771957f773d8ce1c19b0..799c5ba089a00a79ceed7d8636ef765a77f45ed1 100644 (file)
--- a/drivers/ddr/marvell/a38x/ddr3_training.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training.c
@@ -365,6 +365,7 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_
        u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
        struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
        enum hws_ddr_freq freq = tm->interface_params[0].memory_freq;
+       enum mv_ddr_timing timing;
 
        DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
                          ("Init_controller, do_mrs_phy=%d, is_ctrl64_bit=%d\n",
@@ -603,8 +604,12 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_
                                      DUNIT_CTRL_HIGH_REG,
                                      (init_cntr_prm->msys_init << 7), (1 << 7)));
 
+                       timing = tm->interface_params[if_id].timing;
+
                        if (mode_2t != 0xff) {
                                t2t = mode_2t;
+                       } else if (timing != MV_DDR_TIM_DEFAULT) {
+                               t2t = (timing == MV_DDR_TIM_2T) ? 1 : 0;
                        } else {
                                /* calculate number of CS (per interface) */
                                CHECK_STATUS(calc_cs_num
@@ -1268,6 +1273,7 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type,
        u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
        struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
        unsigned int tclk;
+       enum mv_ddr_timing timing = tm->interface_params[if_id].timing;
 
        DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
                          ("dev %d access %d IF %d freq %d\n", dev_num,
@@ -1410,6 +1416,8 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type,
                /* Calculate 2T mode */
                if (mode_2t != 0xff) {
                        t2t = mode_2t;
+               } else if (timing != MV_DDR_TIM_DEFAULT) {
+                       t2t = (timing == MV_DDR_TIM_2T) ? 1 : 0;
                } else {
                        /* Calculate number of CS per interface */
                        CHECK_STATUS(calc_cs_num(dev_num, if_id, &cs_num));

diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h
index 2c589eb3a6558b3cc0233845785071e1e248082a..812224909ae4f66ef0ea88cf395b96b8b71dbcfb 100644 (file)
--- a/drivers/ddr/marvell/a38x/ddr_topology_def.h
+++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h
@@ -64,6 +64,9 @@ struct if_params {
 
        /* operation temperature */
        enum mv_ddr_temperature interface_temp;
+
+       /* 2T vs 1T mode (by default computed from number of CSs) */
+       enum mv_ddr_timing timing;
 };
 
 struct mv_ddr_topology_map {

diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
index ce672e9dd4facb008bc3a8b527132a280fbb0cfb..2070bb38b099a151115cb15400461d0ee26dbc71 100644 (file)
--- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
@@ -674,11 +674,6 @@ static int mv_ddr_sw_db_init(u32 dev_num, u32 board_id)
        dfs_low_freq = DFS_LOW_FREQ_VALUE;
        calibration_update_control = 1;
 
-#ifdef CONFIG_ARMADA_38X
-       /* For a38x only, change to 2T mode to resolve low freq instability */
-       mode_2t = 1;
-#endif
-
        ddr3_tip_a38x_get_medium_freq(dev_num, &medium_freq);
 
        return MV_OK;

diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.h b/drivers/ddr/marvell/a38x/mv_ddr_topology.h
index eb017a1497269757612584cde6b93fe63fc0c491..7bef2d1e0e87b0793e445239bb983de5f6f6a082 100644 (file)
--- a/drivers/ddr/marvell/a38x/mv_ddr_topology.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.h
@@ -36,6 +36,12 @@ enum mv_ddr_temperature {
        MV_DDR_TEMP_HIGH
 };
 
+enum mv_ddr_timing {
+       MV_DDR_TIM_DEFAULT,
+       MV_DDR_TIM_1T,
+       MV_DDR_TIM_2T
+};
+
 enum mv_ddr_timing_data {
        MV_DDR_TCK_AVG_MIN, /* sdram min cycle time (t ck avg min) */
        MV_DDR_TAA_MIN, /* min cas latency time (t aa min) */