// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2015, 2021 Tony Dinh <mibodhi@gmail.com>
+ * Copyright (C) 2015, 2021-2022 Tony Dinh <mibodhi@gmail.com>
* Copyright (C) 2015 Gerald Kerma <dreagle@doukki.net>
*/
#include <common.h>
#include <init.h>
-#include <miiphy.h>
-#include <net.h>
+#include <netdev.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>
#include <asm/global_data.h>
#include <asm/io.h>
-#include "nsa310s.h"
+#include <linux/bitops.h>
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * low GPIO's
+ */
+#define HDD1_GREEN_LED BIT(16)
+#define HDD1_RED_LED BIT(13)
+#define USB_GREEN_LED BIT(15)
+#define USB_POWER BIT(21)
+#define SYS_GREEN_LED BIT(28)
+#define SYS_ORANGE_LED BIT(29)
+
+#define COPY_GREEN_LED BIT(22)
+#define COPY_RED_LED BIT(23)
+
+#define PIN_USB_GREEN_LED 15
+#define PIN_USB_POWER 21
+
+#define NSA310S_OE_LOW (~(0))
+#define NSA310S_VAL_LOW (SYS_GREEN_LED | USB_POWER)
+
+/*
+ * high GPIO's
+ */
+#define HDD2_GREEN_LED BIT(2)
+#define HDD2_POWER BIT(1)
+
+#define NSA310S_OE_HIGH (~(0))
+#define NSA310S_VAL_HIGH (HDD2_POWER)
+
int board_early_init_f(void)
{
/*
return 0;
}
-static int fdt_get_phy_addr(const char *path)
-{
- const void *fdt = gd->fdt_blob;
- const u32 *reg;
- const u32 *val;
- int node, phandle, addr;
-
- /* Find the node by its full path */
- node = fdt_path_offset(fdt, path);
- if (node >= 0) {
- /* Look up phy-handle */
- val = fdt_getprop(fdt, node, "phy-handle", NULL);
- if (val) {
- phandle = fdt32_to_cpu(*val);
- if (!phandle)
- return -1;
- /* Follow it to its node */
- node = fdt_node_offset_by_phandle(fdt, phandle);
- if (node) {
- /* Look up reg */
- reg = fdt_getprop(fdt, node, "reg", NULL);
- if (reg) {
- addr = fdt32_to_cpu(*reg);
- return addr;
- }
- }
- }
- }
- return -1;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-void reset_phy(void)
+int board_eth_init(struct bd_info *bis)
{
- u16 reg;
- u16 phyaddr;
- char *name = "ethernet-controller@72000";
- char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0";
-
- if (miiphy_set_current_dev(name))
- return;
-
- phyaddr = fdt_get_phy_addr(eth0_path);
- if (phyaddr < 0)
- return;
-
- /* set RGMII delay */
- miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
- miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, ®);
- reg |= (MV88E1318_RGMII_RX_CTRL | MV88E1318_RGMII_TX_CTRL);
- miiphy_write(name, phyaddr, MV88E1318_MAC_CTRL_REG, reg);
- miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
-
- /* reset PHY */
- if (miiphy_reset(name, phyaddr))
- return;
-
- /*
- * ZyXEL NSA310S uses the 88E1310S Alaska (interface identical to 88E1318)
- * and has an MCU attached to the LED[2] via tristate interrupt
- */
-
- /* switch to LED register page */
- miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_LED_PG);
- /* read out LED polarity register */
- miiphy_read(name, phyaddr, MV88E1318_LED_POL_REG, ®);
- /* clear 4, set 5 - LED2 low, tri-state */
- reg &= ~(MV88E1318_LED2_4);
- reg |= (MV88E1318_LED2_5);
- /* write back LED polarity register */
- miiphy_write(name, phyaddr, MV88E1318_LED_POL_REG, reg);
- /* jump back to page 0, per the PHY chip documenation. */
- miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
-
- /* set PHY back to auto-negotiation mode */
- miiphy_write(name, phyaddr, 0x4, 0x1e1);
- miiphy_write(name, phyaddr, 0x9, 0x300);
- /* downshift */
- miiphy_write(name, phyaddr, 0x10, 0x3860);
- miiphy_write(name, phyaddr, 0x0, 0x9140);
-
- printf("MV88E1318 PHY initialized on %s\n", name);
+ return cpu_eth_init(bis);
}
-#endif /* CONFIG_RESET_PHY_R */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015
- * Gerald Kerma <dreagle@doukki.net>
- * Tony Dinh <mibodhi@gmail.com>
- */
-
-#ifndef __NSA310S_H
-#define __NSA310S_H
-
-/* low GPIO's */
-#define HDD1_GREEN_LED (1 << 16)
-#define HDD1_RED_LED (1 << 13)
-#define USB_GREEN_LED (1 << 15)
-#define USB_POWER (1 << 21)
-#define SYS_GREEN_LED (1 << 28)
-#define SYS_ORANGE_LED (1 << 29)
-
-#define COPY_GREEN_LED (1 << 22)
-#define COPY_RED_LED (1 << 23)
-
-#define PIN_USB_GREEN_LED 15
-#define PIN_USB_POWER 21
-
-#define NSA310S_OE_LOW (~(0))
-#define NSA310S_VAL_LOW (SYS_GREEN_LED | USB_POWER)
-
-/* high GPIO's */
-#define HDD2_GREEN_LED (1 << 2)
-#define HDD2_POWER (1 << 1)
-
-#define NSA310S_OE_HIGH (~(0))
-#define NSA310S_VAL_HIGH (HDD2_POWER)
-
-/* PHY related */
-#define MV88E1318_PGADR_REG 22
-#define MV88E1318_MAC_CTRL_PG 2
-#define MV88E1318_MAC_CTRL_REG 21
-#define MV88E1318_RGMII_TX_CTRL (1 << 4)
-#define MV88E1318_RGMII_RX_CTRL (1 << 5)
-#define MV88E1318_LED_PG 3
-#define MV88E1318_LED_POL_REG 17
-#define MV88E1318_LED2_4 (1 << 4)
-#define MV88E1318_LED2_5 (1 << 5)
-
-#endif /* __NSA310S_H */
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2015, 2021 Tony Dinh <mibodhi@gmail.com>
+ * Copyright (C) 2015, 2021-2022 Tony Dinh <mibodhi@gmail.com>
* Copyright (C) 2015
* Gerald Kerma <dreagle@doukki.net>
* Luka Perkov <luka.perkov@sartura.hr>
#include "mv-common.h"
-/* environment variables configuration */
-
/* default environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs_root=ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw\0"
/* Ethernet driver configuration */
-#ifdef CONFIG_CMD_NET
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 1
-#endif /* CONFIG_CMD_NET */
-/* SATA driver configuration */
-#ifdef CONFIG_SATA
+/* Support large HDDs for USB and SATA */
#define CONFIG_LBA48
-#endif /* CONFIG_SATA */
+#define CONFIG_SYS_64BIT_LBA
#endif /* _CONFIG_NSA310S_H */
projects / u-boot.git / commitdiff
