]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
imx: imx8m[m/n]_beacon: Enable SPL_DM_SERIAL
authorPeng Fan <peng.fan@nxp.com>
Sat, 11 Jun 2022 12:20:55 +0000 (20:20 +0800)
committerStefano Babic <sbabic@denx.de>
Tue, 14 Jun 2022 19:33:13 +0000 (21:33 +0200)
Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_init to make sure driver
model work.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Adam Ford <aford173@gmail.com> #imx8mm_beacon
Reviewed-by: Fabio Estevam <festevam@denx.de>
Tested-by: Adam Ford <aford173@gmail.com> #imx8mn_beacon
board/beacon/imx8mm/spl.c
board/beacon/imx8mn/spl.c
configs/imx8mm_beacon_defconfig
configs/imx8mn_beacon_2g_defconfig
configs/imx8mn_beacon_defconfig
include/configs/imx8mm_beacon.h
include/configs/imx8mn_beacon.h

index 12266b22a42fcdc1eb2d6b6d33beeeda2e70a843..f92b4c3ed0abc8cd9b2df770ea7748e88a003848 100644 (file)
@@ -59,14 +59,8 @@ int board_fit_config_name_match(const char *name)
 }
 #endif
 
-#define UART_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
 #define WDOG_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
 
-static iomux_v3_cfg_t const uart_pads[] = {
-       IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-       IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
 static iomux_v3_cfg_t const wdog_pads[] = {
        IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
 };
@@ -79,8 +73,6 @@ int board_early_init_f(void)
 
        set_wdog_reset(wdog);
 
-       imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
        return 0;
 }
 
@@ -128,8 +120,6 @@ void board_init_f(ulong dummy)
 
        timer_init();
 
-       preloader_console_init();
-
        /* Clear the BSS. */
        memset(__bss_start, 0, __bss_end - __bss_start);
 
@@ -139,6 +129,8 @@ void board_init_f(ulong dummy)
                hang();
        }
 
+       preloader_console_init();
+
        ret = uclass_get_device_by_name(UCLASS_CLK,
                                        "clock-controller@30380000",
                                        &dev);
index bb51be01c5299780e2c83b266e1d9dc1464072ec..4563446db196884ee19577dc142db4af0a5fcdad 100644 (file)
@@ -68,7 +68,6 @@ int board_fit_config_name_match(const char *name)
 }
 #endif
 
-#define UART_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
 #define WDOG_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
 #define PWM1_PAD_CTRL (PAD_CTL_FSEL2 | PAD_CTL_DSE6)
 
@@ -76,11 +75,6 @@ static iomux_v3_cfg_t const pwm_pads[] = {
        IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL),
 };
 
-static iomux_v3_cfg_t const uart_pads[] = {
-       IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-       IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
 static iomux_v3_cfg_t const wdog_pads[] = {
        IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
 };
@@ -95,7 +89,6 @@ int board_early_init_f(void)
        imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
        set_wdog_reset(wdog);
 
-       imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
        init_uart_clk(1);
 
        return 0;
@@ -114,14 +107,14 @@ void board_init_f(ulong dummy)
 
        timer_init();
 
-       preloader_console_init();
-
        ret = spl_init();
        if (ret) {
                debug("spl_init() failed: %d\n", ret);
                hang();
        }
 
+       preloader_console_init();
+
        enable_tzc380();
 
        /* DDR initialization */
index 417ece1ef8cd4691f0964980db742fb07c685815..e1acf7e8810221cb11dbd4bfc2db6d082dfefbcf 100644 (file)
@@ -125,7 +125,6 @@ CONFIG_SPL_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_CONS_INDEX=2
 CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
 CONFIG_MXC_UART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
index 5b9b3715b34147e5d8d9394fab251fee41190237..cadef45028d9497ec560e02b6fe3652526f10553 100644 (file)
@@ -127,7 +127,6 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_DM_RESET=y
 CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
 CONFIG_MXC_UART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
index b296898d6db7491a618e6d8d3ad4f257a3c3e77b..357109e32e5f0885146858b88ffe4221ea2eac3a 100644 (file)
@@ -131,7 +131,6 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_DM_RESET=y
 CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
 CONFIG_MXC_UART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
index 897eac66b1483fec27a0f5e23d97ecc992d08be5..899d2ec34f9eabf36f74993a000ebb5997aab1bb 100644 (file)
@@ -80,6 +80,4 @@
 #define PHYS_SDRAM                     0x40000000
 #define PHYS_SDRAM_SIZE                0x80000000 /* 2GB DDR */
 
-#define CONFIG_MXC_UART_BASE           UART_BASE_ADDR(2)
-
 #endif
index 99cbc1d07c8fbbac646f5b1d8e3ad38177a29de0..cadad050d0786bf30454c01ef1d68690a424e85d 100644 (file)
@@ -96,6 +96,4 @@
 #define PHYS_SDRAM_SIZE                0x40000000 /* 1GB DDR */
 #endif
 
-#define CONFIG_MXC_UART_BASE           UART_BASE_ADDR(2)
-
 #endif