]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
board: ti: k2g: Add support for K2G ICE with 1GHz Silicon
authorLokesh Vutla <lokeshvutla@ti.com>
Thu, 17 Dec 2020 17:28:07 +0000 (22:58 +0530)
committerLokesh Vutla <lokeshvutla@ti.com>
Tue, 12 Jan 2021 04:51:41 +0000 (10:21 +0530)
Add board detection support for K2G ICE with FlagChip 1GHz silicon.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
board/ti/ks2_evm/board.c
board/ti/ks2_evm/board.h
board/ti/ks2_evm/board_k2g.c
board/ti/ks2_evm/ddr3_k2g.c
board/ti/ks2_evm/mux-k2g.h
include/configs/k2g_evm.h

index c7be54002899aeb4768dcaf669396201c09af8b6..53bc12791d2b3d7bc8e3f104300f67b970cebbd5 100644 (file)
@@ -48,11 +48,11 @@ int dram_init(void)
        gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
                                    CONFIG_MAX_RAM_BANK_SIZE);
 #if defined(CONFIG_TI_AEMIF)
-       if (!board_is_k2g_ice())
+       if (!(board_is_k2g_ice() || board_is_k2g_i1()))
                aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
 #endif
 
-       if (!board_is_k2g_ice()) {
+       if (!(board_is_k2g_ice() || board_is_k2g_i1())) {
                if (ddr3_size)
                        ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
                else
index d0cfbf5a7517ff4fa48b8cefaab8ce2ddcc9a57c..93fc3887f40fd04b09a36d244d596b037aec574d 100644 (file)
@@ -25,6 +25,10 @@ static inline int board_is_k2g_ice(void)
 {
        return board_ti_is("66AK2GIC");
 }
+static inline int board_is_k2g_i1(void)
+{
+       return board_ti_is("66AK2GI1");
+}
 #else
 static inline int board_is_k2g_gp(void)
 {
@@ -34,6 +38,10 @@ static inline int board_is_k2g_ice(void)
 {
        return false;
 }
+static inline int board_is_k2g_i1(void)
+{
+       return false;
+}
 #endif
 
 void spl_init_keystone_plls(void);
index a71024bcbce5cb3fccd21fd3966809a4805d8d51..2be86d6d265a785913f37f37335a82fb0f6ef88b 100644 (file)
@@ -248,7 +248,8 @@ int board_fit_config_name_match(const char *name)
        else if (!strcmp(name, "keystone-k2g-evm") &&
                (board_ti_is("66AK2GGP") || board_ti_is("66AK2GG1")))
                return 0;
-       else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC"))
+       else if (!strcmp(name, "keystone-k2g-ice") &&
+                (board_ti_is("66AK2GIC") || board_is_k2g_i1()))
                return 0;
        else
                return -1;
@@ -322,7 +323,7 @@ int embedded_dtb_select(void)
                             BIT(9));
                setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
                             BIT(9));
-       } else if (board_is_k2g_ice()) {
+       } else if (board_is_k2g_ice() || board_is_k2g_i1()) {
                /* GBE Phy workaround. For Phy to latch the input
                 * configuration, a GPIO reset is asserted at the
                 * Phy reset pin to latch configuration correctly after SoC
@@ -364,6 +365,8 @@ int board_late_init(void)
                env_set("board_name", "66AK2GG1\0");
        else if (board_is_k2g_ice())
                env_set("board_name", "66AK2GIC\0");
+       else if (board_is_k2g_i1())
+               env_set("board_name", "66AK2GI1\0");
 #endif
        return 0;
 }
index 563c5e9950ce71266db6ff64d2f46e22ff8dda3e..3000d7245eb21202a9168f563168acaf197e6f19 100644 (file)
@@ -174,7 +174,7 @@ u32 ddr3_init(void)
        } else if (board_is_k2g_gp()) {
                ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g);
                ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g);
-       } else if (board_is_k2g_ice()) {
+       } else if (board_is_k2g_ice() || board_is_k2g_i1()) {
                ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_512mb);
                ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_512mb);
        }
index 3ecf571c5c37827195560e45a87339fec945afbd..fa6c92cbdf1ed2d2040821e9554686147e969bd5 100644 (file)
@@ -377,7 +377,7 @@ void k2g_mux_config(void)
                configure_pin_mux(k2g_generic_pin_cfg);
        } else if (board_is_k2g_gp() || board_is_k2g_g1()) {
                configure_pin_mux(k2g_evm_pin_cfg);
-       } else if (board_is_k2g_ice()) {
+       } else if (board_is_k2g_ice() || board_is_k2g_i1()) {
                configure_pin_mux(k2g_ice_evm_pin_cfg);
        } else {
                puts("Unknown board, cannot configure pinmux.");
index 83466b9e0cfa9e6d375b7763c67a14cbcddf382b..4471eb4f6a8473daf8b258542a3e068aa5efa0e1 100644 (file)
@@ -35,6 +35,8 @@
                        "setenv name_fdt keystone-k2g-evm.dtb; " \
                "else if test $board_name = 66AK2GIC; then " \
                         "setenv name_fdt keystone-k2g-ice.dtb; " \
+               "else if test $board_name = 66AK2GI1; then " \
+                        "setenv name_fdt keystone-k2g-ice.dtb; " \
                "else if test $name_fdt = undefined; then " \
                        "echo WARNING: Could not determine device tree to use;"\
                "fi;fi;fi;fi; setenv fdtfile ${name_fdt}\0" \