rockchip: boot0: align to 0x20 for armv7 '_start'

The '_start' is using as vector table base address, and will write
to VBAR register, so it needs to be aligned to 0x20 for armv7.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[Updated to current code base:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h b/arch/arm/include/asm/arch-rockchip/boot0.h
index 455d8428d80da336c41ac7565d740f314084a28a..f7c614669cf7716fa0444a0c97d5d8c17d9018e8 100644 (file)
--- a/arch/arm/include/asm/arch-rockchip/boot0.h
+++ b/arch/arm/include/asm/arch-rockchip/boot0.h
@@ -6,12 +6,13 @@
 
 /*
  * Execution starts on the instruction following this 4-byte header
- * (containing the magic 'RK33').
+ * (containing the magic 'RK30', 'RK31', 'RK32' or 'RK33').  This
+ * magic constant will be written into the final image by the rkimage
+ * tool, but we need to reserve space for it here.
  *
  * To make life easier for everyone, we build the SPL binary with
  * space for this 4-byte header already included in the binary.
  */
-
 #ifdef CONFIG_SPL_BUILD
        /*
         * We need to add 4 bytes of space for the 'RK33' at the
@@ -26,6 +27,15 @@
        b reset  /* may be overwritten --- should be 'nop' or a 'b reset' */
 #endif
        b reset
+#if !defined(CONFIG_ARM64)
+       /*
+        * For armv7, the addr '_start' will used as vector start address
+        * and write to VBAR register, which needs to aligned to 0x20.
+        */
+       .align(5)
+_start:
+       ARM_VECTORS
+#endif
 
 #if defined(CONFIG_ROCKCHIP_RK3399) && defined(CONFIG_SPL_BUILD)
        .space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */