board: axs10x: Flush entire cache after programming reset vector

Now when we have support of IOC (IO-Coherency block) cahce operations
on regions are tuned to not be dummy stubs if IOC was found and enabled
in the core. That makes flush_dcache_range() useless for our purposes
here. And since we do need to flush modified reset vector to at least L2
cache (AKA SLC) so other cores will see it via its L1 instruction cache
we're using always functional flush_dcache_all() here.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Marek Vasut <marex@denx.de>

diff --git a/board/synopsys/axs101/axs101.c b/board/synopsys/axs101/axs101.c
index 84ee2bf43de911d1ee4441443ff7f650f18585c8..a5e774b2cf7b26e8d12b801e3e545b6e94666991 100644 (file)
--- a/board/synopsys/axs101/axs101.c
+++ b/board/synopsys/axs101/axs101.c
@@ -54,7 +54,7 @@ void smp_set_core_boot_addr(unsigned long addr, int corenr)
        writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
 
        /* Make sure other cores see written value in memory */
-       flush_dcache_range(RESET_VECTOR_ADDR, RESET_VECTOR_ADDR + sizeof(int));
+       flush_dcache_all();
 }
 
 void smp_kick_all_cpus(void)