return (0x0000ffff & j);
}
-static struct mbus_win windows[] = {
+static const struct mbus_win windows[] = {
/* Window 0: PCIE MEM address space */
{ KW_DEFADR_PCI_MEM, KW_DEFADR_PCI_MEM_SIZE,
KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_MEM },
unsigned int mvebu_sdram_bar(enum memory_bank bank);
unsigned int mvebu_sdram_bs(enum memory_bank bank);
void mvebu_sdram_size_adjust(enum memory_bank bank);
-int mvebu_mbus_probe(struct mbus_win windows[], int count);
+int mvebu_mbus_probe(const struct mbus_win windows[], int count);
void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
unsigned int gpp0_oe, unsigned int gpp1_oe);
int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,
#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
-static struct mbus_win windows[] = {
+static const struct mbus_win windows[] = {
/* SPI */
{ MBUS_SPI_BASE, MBUS_SPI_SIZE,
CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },
unsigned int mvebu_sdram_bar(enum memory_bank bank);
unsigned int mvebu_sdram_bs(enum memory_bank bank);
void mvebu_sdram_size_adjust(enum memory_bank bank);
-int mvebu_mbus_probe(struct mbus_win windows[], int count);
+int mvebu_mbus_probe(const struct mbus_win windows[], int count);
u32 mvebu_get_nand_clock(void);
void __noreturn return_to_bootrom(void);
return 0;
}
-int mvebu_mbus_probe(struct mbus_win windows[], int count)
+int mvebu_mbus_probe(const struct mbus_win windows[], int count)
{
int win;
int ret;
u8 serdes_unit_num;
};
-static struct serdes_unit_data serdes_type_to_unit_info[] = {
+static const struct serdes_unit_data serdes_type_to_unit_info[] = {
{PEX_UNIT_ID, 0,},
{PEX_UNIT_ID, 1,},
{PEX_UNIT_ID, 2,},
{ },
};
-static struct reset_ops mvebu_reset_ops = {
+static const struct reset_ops mvebu_reset_ops = {
.of_xlate = mvebu_reset_of_xlate,
.request = mvebu_reset_request,
.rfree = mvebu_reset_free,