arch: powerpc: update the eLBC IP input clock

eLBC IP clock is always a constant divisor of platform clock
pre-defined per SoC. Clock ratio register (LCRR) used in
current implementation governs eLBC IP output cloc.

Update sys_info->freq_localbus to represent eLBC input clock with
value constant divisor of platform clock.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/README b/README
index 9fda38109de737c51b25cbefca338bda8a7a6604..b27e7577dfdce0428b6f9628998049f9c1666e56 100644 (file)
--- a/README
+++ b/README
@@ -507,6 +507,9 @@ The following options need to be configured:
                CONFIG_SYS_FSL_IFC_CLK_DIV
                Defines divider of platform clock(clock input to IFC controller).
 
+               CONFIG_SYS_FSL_LBC_CLK_DIV
+               Defines divider of platform clock(clock input to eLBC controller).
+
                CONFIG_SYS_FSL_PBL_PBI
                It enables addition of RCW (Power on reset configuration) in built image.
                Please refer doc/README.pblimage for more details

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index c06a4db8fc3ab9ecce9577c072ab1c82bd0b4420..592b58171ada79c6b66ee8c704de9bf3bc14452a 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1337,6 +1337,24 @@ config SYS_FSL_IFC_CLK_DIV
                Defines divider of platform clock(clock input to
                IFC controller).
 
+config SYS_FSL_LBC_CLK_DIV
+       int "Divider of platform clock"
+       depends on FSL_ELBC || ARCH_MPC8540 || \
+               ARCH_MPC8548 || ARCH_MPC8541 || \
+               ARCH_MPC8555 || ARCH_MPC8560 || \
+               ARCH_MPC8568
+
+       default 2 if    ARCH_P2041      || \
+                       ARCH_P3041      || \
+                       ARCH_P4080      || \
+                       ARCH_P5020      || \
+                       ARCH_P5040
+       default 1
+
+       help
+               Defines divider of platform clock(clock input to
+               eLBC controller).
+
 source "board/freescale/b4860qds/Kconfig"
 source "board/freescale/bsc9131rdb/Kconfig"
 source "board/freescale/bsc9132qds/Kconfig"

diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index adba0925b7f6d02537abd90984e031a87052230d..cb8281e19e13e15204cfe6fb129149308207a342 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -607,32 +607,8 @@ void get_sys_info(sys_info_t *sys_info)
 #endif /* CONFIG_FSL_CORENET */
 
 #if defined(CONFIG_FSL_LBC)
-       uint lcrr_div;
-#if defined(CONFIG_SYS_LBC_LCRR)
-       /* We will program LCRR to this value later */
-       lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
-#else
-       lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
-#endif
-       if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
-#if defined(CONFIG_FSL_CORENET)
-               /* If this is corenet based SoC, bit-representation
-                * for four times the clock divider values.
-                */
-               lcrr_div *= 4;
-#elif !defined(CONFIG_ARCH_MPC8540) && !defined(CONFIG_ARCH_MPC8541) && \
-       !defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_ARCH_MPC8560)
-               /*
-                * Yes, the entire PQ38 family use the same
-                * bit-representation for twice the clock divider values.
-                */
-               lcrr_div *= 2;
-#endif
-               sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
-       } else {
-               /* In case anyone cares what the unknown value is */
-               sys_info->freq_localbus = lcrr_div;
-       }
+       sys_info->freq_localbus = sys_info->freq_systembus /
+                                               CONFIG_SYS_FSL_LBC_CLK_DIV;
 #endif
 
 #if defined(CONFIG_FSL_IFC)

diff --git a/arch/powerpc/cpu/mpc86xx/speed.c b/arch/powerpc/cpu/mpc86xx/speed.c
index 05f23db457884edca6c05aee6b0a15f55ed6de76..51b47b823bd6d68bab9bdd81a5c0dae3aa5d2f4f 100644 (file)
--- a/arch/powerpc/cpu/mpc86xx/speed.c
+++ b/arch/powerpc/cpu/mpc86xx/speed.c
@@ -24,7 +24,6 @@ void get_sys_info(sys_info_t *sys_info)
        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
        volatile ccsr_gur_t *gur = &immap->im_gur;
        uint plat_ratio, e600_ratio;
-       uint lcrr_div;
 
        plat_ratio = (gur->porpllsr) & 0x0000003e;
        plat_ratio >>= 1;
@@ -78,19 +77,7 @@ void get_sys_info(sys_info_t *sys_info)
                break;
        }
 
-#if defined(CONFIG_SYS_LBC_LCRR)
-       /* We will program LCRR to this value later */
-       lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
-#else
-       lcrr_div = in_be32(&immap->im_lbc.lcrr) & LCRR_CLKDIV;
-#endif
-       if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
-               sys_info->freq_localbus = sys_info->freq_systembus
-                                                       / (lcrr_div * 2);
-       } else {
-               /* In case anyone cares what the unknown value is */
-               sys_info->freq_localbus = lcrr_div;
-       }
+       sys_info->freq_localbus = sys_info->freq_systembus;
 }